Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer having a main surface, the main surface being provided with a trench which has a bottom portion and a sidewall inclined with respect to the main surface; a gate insulating film covering each of the bottom portion and the sidewall; a gate electrode provided at least on the gate insulating film; and an upper insulating film provided on the main surface and having a part which protrudes into the trench.

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Abstract: A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

Abstract: Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: A semiconductor device includes: an IGBT section including a vertical IGBT; and a diode section arranged along the IGBT section and including a diode. The diode section includes a hole injection reduction layer having a first conductivity type and arranged in an upper layer portion of a drift layer, extending to a depth deeper than an anode region constituted by a second conductivity type region in the diode section, having an impurity concentration lower than an impurity concentration of the anode region and higher than an impurity concentration of the drift layer.

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a semiconductor substrate, forming a porous low-k dielectric layer on the semiconductor substrate, forming a through-hole and a trench of a copper interconnect structure, performing a helium plasma treatment on an exposed surface of the porous low-k dielectric layer, performing a nitrogen plasma treatment on the exposed surface of the porous low-k dielectric layer to form a silicon nitride layer, performing an argon plasma treatment on the silicon nitride layer, and forming a diffusion barrier layer on bottoms and sidewalls of the through-hole and the trench of the copper interconnect structure. Through the successive helium, nitrogen and argon plasma treatments, the low-k dielectric layer has a smooth and dense surface that increases the adhesion strength between the low-k dielectric layer and the diffusion barrier layer to improve reliability and yield of the semiconductor device.

Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type layer is formed on or in the p-doped layer. The n-type layer includes ZnO on the p-doped layer to form an electronic device.

Abstract: An optoelectronic component includes a substrate, a connecting element applied on the substrate and a layer sequence that emits electromagnetic radiation. The layer sequence is applied on the connecting element. The connecting element includes at least one connecting material that has an oriented molecular configuration. The connecting element has at least one parameter that is anisotropic.

Abstract: An integrated circuit includes 3D memory blocks and 3D capacitor blocks. The 3D capacitor comprises a plurality of stacks of conductive strips alternating with insulating strips, and a first terminal connected to conductive strips in consecutive levels in one or more stacks, whereby the conductive strips act as a first plate of the 3D capacitor. A second terminal is insulated from the first terminal, either connected to conductive strips in consecutive levels in another or other stacks, or connected to a plurality of pillars. No intervening conductive strip is disposed between the conducive strips in consecutive levels.

Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.

Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.

Abstract: A semiconductor device includes a substrate, a pair of source/drain units, and a semiconductor sheet unit. The substrate includes a well region. The source/drain units are disposed above the well region. The semiconductor sheet unit is disposed substantially vertically, interconnects the source/drain units, and defines a cross-sectional shape unit in a top view. The cross-sectional shape unit includes a plurality of cross-sections that have substantially the same shape and different sizes.

Abstract: Provided is a composite substrate which has a high-performance semiconductor layer. A composite substrate of the present invention comprises: a supporting substrate which is formed of an insulating material; a semiconductor layer which is formed of a single crystal semiconductor that is superposed on and joined to the supporting substrate; and interfacial inclusions which are present in the interface between the supporting substrate and the semiconductor layer at a density of 1012 atoms/cm2 or less, and which are formed of a metal element that is different from the constituent elements of the supporting substrate and the semiconductor layer.

Abstract: High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage.

Abstract: A solid-state imaging device includes a photoelectric conversion section configured to generate photocharges and a transfer gate that transfers the photocharges to a semiconductor region. A method for driving a unit pixel includes a step of accumulating photocharges in a photoelectric conversion section and a step of accumulating the photocharges in a semiconductor region. A method of forming a solid-state imaging device includes implanting ions into a well layer through an opening in a mask, implanting additional ions into the well layer through an opening in another mask, and implanting other ions into the well layer through an opening in yet another mask. An electronic device includes the solid-state imaging device.

Abstract: An integrated circuit includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, at least one first trench extending into the first semiconductor substrate from the first surface and having a first depth, at least one second trench extending into the first semiconductor substrate from the first surface and having a second depth greater than the first depth, a thinned semiconductor region with a first recessed region extending in the first semiconductor substrate from the second surface and having a first thickness, a second recessed region in the first semiconductor substrate extending from the second surface to the first surface, and a bulk dielectric layer covering the second surface of the first semiconductor substrate.