Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.

Abstract: A micromechanical component includes a sensor chip and a cap chip connected to the sensor chip. A cavity is formed between the sensor chip and the cap chip. The sensor chip has a movable element situated in the cavity. The cap chip has a wiring level containing an electrically conductive electrode. The cap chip has a getter element situated in the cavity.

Abstract: A semiconductor device includes a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.

Abstract: A storage device includes a first wiring layer, a second wiring layer above the first wiring layer, a third wiring layer above the second wiring layer, a first contact in electrical contact with the first and third wiring layers and electrically insulated from the second wiring layer, a second contact in electrical contact with the first and second wiring layers and electrically insulated from the third wiring layer, and an insulating layer in contact with the second contact and above the third wiring layer, the first contact, and the second contact.

Abstract: Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices.

Abstract: After forming a seed layer over a first end of a sacrificial semiconductor layer composed of silicon germanium, a remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the seed layer that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.

Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

Abstract: A method of fabricating a vertical field effect transistor includes forming fins from a portion of a substrate. At least a first fin of the fins is associated with a first device, at least a second fin of the fins is associated with a second device. The method includes forming alternating pillars of a first polymer and a second polymer on the substrate, removing the pillars of the second polymer except between two or more fins of a same device, and forming the substrate pillars below the pillars of the first polymer. The etching creates a deep trench between the first fin and the second fin. Removing the pillars of the first polymer and any remaining ones of the pillars of the second polymer is followed by performing an oxide fill to fill the deep trench and gaps between the pillars of the substrate with oxide.

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

Abstract: There are provided a chip-on-board type light emitting device package capable of improving structural reliability and heat-dissipating efficiency and reducing a manufacturing cost, and a method for manufacturing the same. The chip-on-board type light emitting device package includes: a dual frame including a base frame on which a plurality of light emitting devices are mounted and an electrode frame positioned above the base frame so as to be spaced apart from the base frame and including two electrodes separated from each other; and a molding part coupled to the dual frame so that the base frame and the electrode frame are spaced apart from each other and having an opening through which light generated in the plurality of light emitting devices is to be emitted, wherein the base frame has a through-hole through which the electrode frame is exposed.

Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence and a carrier substrate. A first and a second electrical contact layer are arranged at least regionally between the carrier substrate and the semiconductor layer sequence and are electrically insulated from each other by an electrically insulating layer. A mirror layer is arranged between the semiconductor layer sequence and the carrier substrate. The semiconductor chip comprises a transparent encapsulation layer covering side surfaces of the semiconductor layer sequence, side surfaces of the mirror layer and side surfaces of the electrically insulating layer facing towards the side surfaces of the semiconductor chip.

Abstract: A display device and a method for manufacturing the same, the display device including a substrate that includes a first area and a second area; a first pixel electrode on the first area of the substrate; a first organic layer on the first pixel electrode, the organic layer including a first light emitting layer; a first counter electrode on the first organic layer; an auxiliary layer on the first counter electrode at the first area of the substrate; a second pixel electrode on the second area of the substrate; a second organic layer on the second pixel electrode, the second organic layer including a second light emitting layer; a second counter electrode on the second organic layer; and an upper reflective layer on the second counter electrode at the second area of the substrate.

Abstract: A thin film transistor, a pixel structure, an array substrate, a display device, a method for manufacturing a thin film transistor, and a method for manufacturing a pixel structure are disclosed. The thin film transistor includes a gate electrode, a source electrode and a drain electrode, wherein a first passivation layer made from an aluminum oxide material is provided on the source electrode and the drain electrode, and an active layer made from an aluminum oxide material doped with ions is provided in a region of the first passivation layer corresponding to the gate electrode. Since the first passivation layer as insulation material is doped with the ions to form an active layer, the etching stop layer may be omitted, thereby simplifying the structure of the thin film transistor.

Abstract: MEMS devices and methods for forming the same are provided. A first metal interconnect structure is formed on a first semiconductor substrate to connect to a CMOS control circuit in the first semiconductor substrate. A bonding layer having a cavity is formed on the first metal interconnect structure, and then bonded with a second semiconductor substrate. A conductive plug passes through a first region of the second semiconductor substrate, through the bonding layer, and on the first metal interconnect structure. A second metal interconnect structure includes a first end formed on the first region of the second semiconductor substrate, and a second end connected to the conductive plug. Through-holes are disposed through a second region of the second semiconductor substrate and through a top portion of the bonded layer that is on the cavity to leave a movable electrode to form the MEMS device.

Abstract: A method for fabricating a semiconductor device includes forming a dielectric layer over a substrate, forming an etch-stop-layer (ESL) over the dielectric layer, forming a first patterned hard mask (HM) defining a first trench over the ESL, forming a second trench extending through the ESL and the dielectric layer. The second trench is adjacent the first trench. The method also includes filling in the first trench and the second trench with a first material layer, extending the first trench through the ESL and the dielectric layer while the first material layer is filled in the second trench to form an extended first trench, forming a first metal line within the extended first trench, forming a capping layer over the first metal line and removing a portion of the first metal line to form a first cut by using the ESL and the first material layer as an etch mask.

Abstract: A semiconductor device having good characteristics without variation and a method of manufacturing the same are provided. A part of a conductive layer for a floating gate is removed by using a spacer insulating film, a first insulating film, and a second insulating film as a mask. A floating gate having a tip portion is formed from the conductive layer for the floating gate, and a part of an insulating layer for a gate insulating film is exposed from the floating gate. The tip portion of the floating gate is further exposed by selectively removing the second insulating film among the second insulating film, the insulating layer for the gate insulating film, and the spacer insulating film.

Abstract: Substrate based light emitter devices, components, and related methods are disclosed. In some aspects, light emitter components can include a substrate and a plurality of light emitter devices provided over the substrate. Each device can include a surface mount device (SMD) adapted to mount over an external substrate or heat sink. In some aspects, each device of the plurality of devices can include at least one LED chip electrically connected to one or more traces and at least one pair of bottom contacts adapted to mount over a surface of external substrate. The component can further include a continuous layer of encapsulant disposed over each device of the plurality of devices. Multiple devices can be singulated from the component.

Abstract: The present invention provides a semiconductor structure, includes a substrate, a dielectric layer disposed on the substrate, a first gate structure and a second gate structure disposed in the dielectric layer, a hard mask disposed in the dielectric layer, where the hard mask covers a sidewall of the first gate structure, and covers the second gate structure, and a contact structure disposed in the dielectric layer. The contact structure at least crosses over the hard mask. The contact structure includes a first contact portion and a second contact portion. The first contact portion contacts the first gate structure directly, the second contact portion contacts the substrate directly, and the hard mask is disposed between the first contact portion and the second contact portion.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.