Abstract: This invention provides a high-efficiency light-emitting device and the manufacturing method thereof The high-efficiency light-emitting device includes a substrate; a reflective layer; a bonding layer; a first semiconductor layer; an active layer; and a second semiconductor layer formed on the active layer. The second semiconductor layer includes a first surface having a first lower region and a first higher region.

Abstract: An optoelectronic semiconductor device in accordance with an embodiment of present invention includes a conversion unit having a first side; an electrical connector; a contact layer having an outer perimeter; and at least three successive discontinuous-regions formed along the outer perimeter and having at least one different factor; wherein the electrical connector, the contact layer, and the discontinuous-regions are formed on the first side of the conversion unit.

Abstract: An organic light emitting diode (OLED) display includes: a substrate; a first semiconductor layer and a second semiconductor layer separated from each other on a same surface of the substrate, a first insulating layer on the first semiconductor layer and the second semiconductor layer, a first gate electrode and a second gate electrode respectively overlapping the first semiconductor layer and the second semiconductor layer, a second insulating layer on the first gate electrode and the second gate electrode; a first storage electrode overlapping the first gate electrode on the second insulating layer, a third insulating layer on the first storage electrode, and a second storage electrode overlapping the first storage electrode on the third insulating layer.

Abstract: Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.

Abstract: In accordance with the present invention, there is provided a semiconductor package wherein a metal lid of the package is used as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to an internal die mounting pad of either a leadframe or an alternative type of substrate. Appropriate interconnect methods between the lid, the die pad, and the ground connections exterior to the semiconductor package include, but are not restricted to, conductive adhesives, wire bonding, bumps, tabs, or similar techniques.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.

Abstract: A mechanism for reducing stiction in a MEMS device by decreasing surface area between two surfaces that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of one or both of the surfaces. The increased roughness is provided by forming a micro-masking layer on a sacrificial layer used in formation of the MEMS device, and then etching the surface of the sacrificial layer. The micro-masking layer can be formed using nanoclusters. When a next portion of the MEMS device is formed on the sacrificial layer, this portion will take on the roughness characteristics imparted on the sacrificial layer by the etch process. The rougher surface decreases the surface area available for contact in the MEMS device and, in turn, decreases the area through which stiction can be imparted.

Abstract: Disclosed is a light emitting device including a support substrate, a transistor unit disposed at one side of the upper surface of the support substrate, a light emitting device unit disposed at the other side of the upper surface of the support substrate, and an insulating layer disposed between the transistor unit and the light emitting device unit and between the support substrate and the transistor unit and isolating the transistor unit from the light emitting device unit.

Abstract: Getter structure comprising a substrate and at least one getter material-based layer mechanically connected to the substrate by means of at least one support, in which the surface of the support in contact with the substrate is smaller than the surface of a first face of the getter material layer, in which said first face is in contact with the support, and a second face of the getter material layer, opposite said first face is at least partially exposed.

Abstract: A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling, and is further diced at the fixed clock-cycle distance, and flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device.

Abstract: The method includes forming a metal interconnection layer and a first interlayer insulating layer on a semiconductor substrate, forming a reservoir capacitor region by etching the first interlayer insulating layer to expose the metal interconnection layer, forming a barrier metal layer on the reservoir capacitor region, forming a sacrificial insulating layer on the barrier metal layer in a lower portion of the reservoir capacitor region, performing a pre-cleaning process to remove the barrier metal layer on a sidewall of the reservoir capacitor region, and removing the sacrificial insulating layer.

Abstract: A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.

Abstract: In one embodiment a semiconductor package includes a metal lid configured as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to a metalized area located on the surface of the active circuitry, or to an additional metalized die. Appropriate interconnect methods between the lid and the metalized die or metalized area include, but are not restricted to, wire bonding, bumps, tabs, or similar techniques.

Abstract: Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.

Abstract: A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well.

Abstract: A silicon-on-diamond (SOD) transistor includes a silicon-based substrate, a diamond insulating layer over the silicon-based substrate, a silicon-based insulating layer directly over and in contact with the diamond insulating layer, a body over the silicon-based insulating layer, and a gate over the body. The structure of the SOD transistor provides improved drain induced barrier lowering (DIBL) in fully-depleted SOD transistors by using a second, silicon-based insulating layer.

Abstract: A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

Abstract: A light-emitting device includes a first semiconductor layer; an active layer formed on the first semiconductor layer; a second semiconductor layer formed on the active layer; and a first pad formed on the second semiconductor layer, wherein the second semiconductor layer comprises a first region right under the first pad and a plurality of voids formed in the first region, wherein the region outside the first region in the second semiconductor layer is devoid of voids, and an area of the first region is smaller than that of the first pad in top view and the area of the first pad is smaller than that of the second semiconductor layer in top view, and the light emitted from the active layer is extracted from a top surface of the second semiconductor layer opposite the first semiconductor layer.

Abstract: Provided is a method and apparatus for focusing sound using an array speaker system. The method includes generating a plurality of delayed signals to be focused to a predetermined position from an input signal, filtering a low-frequency signal having a frequency that is lower than a reference frequency from the delayed signals, generating low-frequency focusing signals divided into 2 groups by adjusting a gain of the filtered low-frequency signal, and applying the low-frequency focusing signals divided into the 2 groups to speaker units of the array speaker system at both sides with respect to a center portion of the array speaker system and outputting the low-frequency focusing signals through the speaker units. In this way, the performance of sound focusing for the low-frequency signal can be improved and thus a listener located a predetermined distance from and in a predetermined direction relative to the array speaker system can clearly listen to the low-frequency focusing signals.

Abstract: A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure.