Abstract: To provide a method for manufacturing a lightweight light-emitting device having a light-emitting region on a curved surface. The light-emitting region is provided on a curved surface in such a manner that a light-emitting element is formed on a flexible substrate supported in a plate-like shape and the flexible substrate deforms or returns.

Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.

Abstract: A smart window controller includes circuitry configured to establish a representative model of one or more building zones based on occupancy, construction, lighting, or cooling properties of a building. A lighting control strategy is implemented for the one or more building zones based on the representative model or one or more user preferences input at a first user interface screen of an external device. Automatic operations of one or more smart windows, cooling systems, or artificial lighting systems are controlled based on trigger points associated with the lighting control strategy, and a performance level of the lighting control strategy for the one or more building zones is determined based on one or more predetermined financial metrics.

Abstract: A smart window controller includes circuitry configured to establish a representative model of one or more building zones based on occupancy, construction, lighting, or cooling properties of a building. A lighting control strategy is implemented for the one or more building zones based on the representative model or one or more user preferences input at a first user interface screen of an external device. Automatic operations of one or more smart windows, cooling systems, or artificial lighting systems are controlled based on trigger points associated with the lighting control strategy, and a performance level of the lighting control strategy for the one or more building zones is determined based on one or more predetermined financial metrics.

Abstract: A smart window controller includes circuitry configured to establish a representative model of one or more building zones based on occupancy, construction, lighting, or cooling properties of a building. A lighting control strategy is implemented for the one or more building zones based on the representative model or one or more user preferences input at a first user interface screen of an external device. Automatic operations of one or more smart windows, cooling systems, or artificial lighting systems are controlled based on trigger points associated with the lighting control strategy, and a performance level of the lighting control strategy for the one or more building zones is determined based on one or more predetermined financial metrics.

Abstract: The present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes SiGe. Then, a first metal oxide layer is formed on the semiconductor substrate. Then, at least one second metal oxide layer and at least one third metal oxide layer are alternately stacked on the first metal oxide layer, thereby forming a nanolaminate structure. And, a conductive gate layer is formed on the nanolaminate structure.

Abstract: This invention relates to a method for using a multivariate statistical control process to reduce the variation of an additively manufactured part or object. The invention also relates to a system and software that can be used to implement the method in additive manufacturing devices or apparatuses.

Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.

Abstract: There is provided a method of laser-processing a device wafer with a laser beam applied thereto. The device wafer has a face side having thereon a plurality of crossing projected dicing lines and devices formed in respective areas demarcated by the projected dicing lines. The method includes a covering step of supplying the face side of the device wafer with water and a powdery protective film agent to cover the face side with an aqueous solution in which the powdery protective film agent is dispersed, a protective film forming step of evaporating the water content of the aqueous solution to form a protective film on the face side, and a laser processing step of applying a laser beam having a wavelength that is absorbable by the device wafer to the device wafer along the projected dicing lines to form laser-processed grooves in the device wafer along the projected dicing lines.

Abstract: A method of making a semiconductor device can include providing a semiconductor die comprising a front surface comprising a gate pad and a source pad, the semiconductor die further comprising a back surface opposite the front surface, the back surface comprising a drain. A gate stud may be formed over and coupled to the gate pad. A source stud may be formed over and coupled to the source pad. An encapsulant may be formed over the semiconductor die. A through mold interconnect may extend between opposing first and second surfaces of the encapsulant. An RDL may be coupled to the gate stud, the source stud, and to the through mold interconnect. A land pad may be formed over the back surface of the semiconductor die and be coupled to the drain after singulating the semiconductor die from its native wafer and after forming the encapsulant over the semiconductor die.

Abstract: A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.

Abstract: In a method of manufacturing a semiconductor device, a first layer containing a Si1-xGex layer doped with phosphorous is formed over an n-type semiconductor layer, a metal layer containing a metal material is formed over the first layer, and a thermal process is performed to form an alloy layer including Si, Ge and the metal material.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Abstract: A half-bridge power semiconductor module includes an insulating wiring board including a positive-electrode wiring conductor, a bridge wiring conductor, and a negative-electrode wiring conductor arranged on or above a single insulating plate in such a way as to be electrically insulated from each other. The back-surface electrodes of a high-side power semiconductor device and a low-side power semiconductor device are joined to the front sides of the positive-electrode wiring conductor and the bridge wiring conductor. Front-surface electrodes of the high-side power semiconductor device and the low-side power semiconductor device are connected to the bridge wiring conductor and the negative-electrode wiring conductor by a plurality of bonding wires and a plurality of bonding wires.

Abstract: A semiconductor light emitting device includes a light emitting structure having a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, a transparent electrode layer on the second conductivity-type semiconductor layer, and a reflective electrode structure on the transparent electrode layer that includes a light-transmitting insulating layer on the transparent electrode layer with insulating patterns, portions of sides of the insulating patterns being open, and a contact region of the transparent electrode layer being defined by a region between the insulating patterns, air gaps between the transparent electrode layer and the insulating patterns, the air gaps extending in the open portions of the sides of the insulating patterns, and a reflective electrode layer on the insulating patterns to cover the open portions of the insulating patterns, the reflective electrode layer being connected to the contact region of the transparent electrode layer.

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The second chip is between the first chip and the third chip. The chip package structure includes a first molding layer surrounding the first chip. The chip package structure includes a second molding layer surrounding the second chip. The chip package structure includes an insulating layer between the first molding layer and the second molding layer and between the first chip and the second chip. A side wall of the first molding layer, a side wall of the second molding layer, and a side wall of the insulating layer are substantially coplanar. The chip package structure includes a third molding layer surrounding the third chip, the first molding layer, the second molding layer, and the insulating layer.

Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

Abstract: A semiconductor device includes a plurality of gate spacers, a gate conductor, and first and semiconductor features. The gate conductor is between the gate spacers. The first semiconductor feature underlies the gate conductor and has impurities therein. The second semiconductor feature underlies at least one of the gate spacers and substantially free from the impurities of the first semiconductor feature.