Abstract: A display panel and a display device are provided. The display panel includes: a plurality of pixel circuits arranged in a matrix; a data line extending in a first direction and being electrically connected to the plurality of pixel circuits; a power signal line extending in the first direction and being electrically connected to the plurality of pixel circuits; an inorganic passivation layer located on surfaces, facing toward a light-emitting surface of the display panel, of the data line and the power signal line; and an anti-crosstalk structure. An orthographic projection of at least partial region of the anti-crosstalk structure on a plane of the display panel is located between an orthographic projection of the data line and an orthographic projection of the power signal line on the plane of the display panel.

Abstract: Provided is an optical semiconductor element in which an unbonded portion between an optical semiconductor chip and a submount is made small, heat dissipation efficiency becomes high, and service life can be made long. The optical semiconductor element can include: a submount; a submount electrode provided on a mounting surface of the submount and having a rectangular shape as a whole; and a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the submount electrode via a bonding layer. The chip electrode has a shape with chipped corners corresponding to four corners of the submount electrode, which has an exposed surface that is a portion exposed from the chip electrode at the four corners and bonded to the chip electrode to coincide with each other. The bonding layer extends to all the four corners of the exposed surface.

Abstract: A p-type base region is configured by a p?-type channel region and a p-type high-impurity-concentration region adjacent to the channel region in a horizontal direction. A point having a highest impurity concentration in the high-concentration region is located at a position separated from a lower surface of an n++-type source region. The impurity concentration in the high-impurity-concentration region decreases toward the front surface of the semiconductor substrate and the rear surface of the semiconductor substrate in the depth direction. The impurity concentration in the high-impurity-concentration region decreases toward the low-impurity-concentration region in a direction parallel to the front surface of the semiconductor substrate.

Abstract: A display may have an array of pixels. Each pixel may have a light-emitting diode such as an organic light-emitting diode or may be formed from other pixel structures such as liquid crystal display pixel structures. The pixels may emit light such as red, green, and blue light. An angle-of-view adjustment layer may overlap the array of pixels. During operation, light from the pixels passes through the angle-of-view adjustment layer to a user. The viewing angle for the user is enhanced as the angular spread of the emitted light from the pixels is enhanced by the angle-of-view adjustment layer. The angle-of-view adjustment layer may be formed from holographic structures recorded by applying laser beams to a photosensitive layer or may be formed from a metasurface that is created by patterning nanostructures on the display using printing, photolithography, or other patterning techniques.

Abstract: A control system is disclosed that includes a room controller transmitting signals to both a shade control network and a light control network, directing that motorized roller shades and dimmable lights be set to desired intensity levels. The control system further includes an intelligent hub that provides a trickle-charge re-charge current via power-over-Ethernet cables to batteries associated with each of the motorized roller shades for re-charging the batteries, thereby eliminating power supplies being installed within walls. The intelligent hub provides for communication with the room controller based on streaming protocol and with the shade control network based on event-based protocol. A computer running user interface software may be connected to the system to facilitate programming.

Abstract: Circuits are described that use metallization on both sides techniques to integrate two different types of non-volatile embedded memory devices within a single monolithic integrated circuit device. In an embodiment, a monolithic integrated circuit structure is provided that includes a device layer having one or more logic transistors. A front side interconnect layer is provided above the device layer, as seen in a vertical cross-section taken through the monolithic integrated circuit from top to bottom. A back side interconnect layer is provided below the device layer, as seen in the vertical cross-section. A first type of non-volatile memory device is provided in the front side interconnect layer, and a second type of non-volatile memory device different from the first type of non-volatile memory device is provided in the back side interconnect layer. A back side contact may be used to connect the device layer to a back side interconnect layer.

Abstract: A household appliance includes a housing; a treating chamber located within the housing and having an access opening; a closure element movable relative to the access opening between opened and closed positions to selectively provide access to the treating chamber through the access opening; a controller associated with the housing and implementing a treating cycle on at least one item in the treating chamber; and a human-machine interface. The HMI includes a first portion associated with the housing and a second portion associated with the closure element. The first portion includes non-touch sensitive indicia. The second portion includes an electrically conductive layer having a touch-sensitive area corresponding to the indicia of the first portion and is arranged to be in register with a corresponding selection area when the closure element is in the closed position.

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

Abstract: A method for processing a silicon carbide wafer includes implanting ions into the silicon carbide wafer to form an absorption layer in the silicon carbide wafer. The absorption coefficient of the absorption layer is at least 100 times the absorption coefficient of silicon carbide material of the silicon carbide wafer outside the absorption layer, for light of a target wavelength. The silicon carbide wafer is split along the absorption layer at least by irradiating the silicon carbide wafer with light of the target wavelength to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor substrate including a high-frequency-block group and a low-power-block group; high-frequency-type logic standard cells located on the high-frequency-block group, and having a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power; low-power-type logic standard cells located on the low-power-block group, and having a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power. The high-frequency-type cell height is higher than the low-power-type cell height. The high-frequency-type operating frequency is greater than the low-power-type operating frequency. The high-frequency-type power is greater than the low-power-type power. The high-frequency-type logic standard cells include high-frequency-type fins, and the low-power-type logic standard cells include low-power-type fins.

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Abstract: An organic light emitting display device includes a substrate, a semiconductor pattern disposed on the substrate, a conductive line disposed in a different layer from the semiconductor pattern, a pixel electrode disposed on the conductive line and on the semiconductor pattern, and a connection electrode disposed in a same layer as the pixel electrode. The connection electrode may be connected to the semiconductor pattern and the conductive line.

Abstract: The present disclosure is drawn to wirebonding for optical engines having side-mounted optoelectronic components. An integrated circuit is mounted on a first surface of a substrate block, and an optoelectronic component is positioned on a second surface of the substrate block and is oriented to emit light in a direction parallel to a plane defined by the first surface. A wirebond is drawn between the integrated circuit and a base substrate on which the substrate block is mounted. A optoelectronic component is then contacted with the wirebond, and a portion of the wirebond between the optoelectronic component and the base substrate is removed.

Abstract: A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 ?m.

Abstract: A smart window controller includes circuitry configured to establish a representative model of one or more building zones based on occupancy, construction, lighting, or cooling properties of a building. A lighting control strategy is implemented for the one or more building zones based on the representative model or one or more user preferences input at a first user interface screen of an external device. Automatic operations of one or more smart windows, cooling systems, or artificial lighting systems are controlled based on trigger points associated with the lighting control strategy, and a performance level of the lighting control strategy for the one or more building zones is determined based on one or more predetermined financial metrics.

Abstract: A system includes an image sensor structure and a flow cell. The image sensor structure includes an image layer disposed over a base substrate. A device stack is disposed over the image layer. A bond pad is disposed in the device stack. A passivation stack is disposed over the device stack and the bond pad. An array of nanowells is disposed in a top layer of the passivation stack. A through-silicon via (TSV) is in electrical contact with the bond pad. The TSV extends through the base substrate. A redistribution layer (RDL) is disposed on a bottom surface of the base substrate. The RDL is in electrical contact with the TSV. The flow cell is disposed upon the top layer of the passivation stack to form a flow channel therebetween. The flow channel is disposed over the array of nanowells and the bond pad.

Abstract: A semiconductor device including a transistor and a wiring electrically connected to the transistor each of which has excellent electrical characteristics because of specific structures thereover is provided. A first conductive film, a first insulating film over the first conductive film, a second conductive film over the first insulating film, a second insulating film over the second conductive film, a third conductive film electrically connected to the first conductive film through an opening provided in the first insulating film and the second insulating film, and a third insulating film over the third conductive film are provided. The third conductive film includes indium, tin, and oxygen, and the third insulating film includes silicon and nitrogen and the number of ammonia molecules released from the third insulating film is less than or equal to 1×1015 molecules/cm3 by thermal desorption spectroscopy.

Abstract: To provide a method for manufacturing a lightweight light-emitting device having a light-emitting region on a curved surface. The light-emitting region is provided on a curved surface in such a manner that a light-emitting element is formed on a flexible substrate supported in a plate-like shape and the flexible substrate deforms or returns.

Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.

Abstract: A smart window controller includes circuitry configured to establish a representative model of one or more building zones based on occupancy, construction, lighting, or cooling properties of a building. A lighting control strategy is implemented for the one or more building zones based on the representative model or one or more user preferences input at a first user interface screen of an external device. Automatic operations of one or more smart windows, cooling systems, or artificial lighting systems are controlled based on trigger points associated with the lighting control strategy, and a performance level of the lighting control strategy for the one or more building zones is determined based on one or more predetermined financial metrics.