Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Abstract: The present invention discloses a dual wavelength light emitting device comprising: a first light emitting device, configured to emit first kind of light; and a second light emitting device, configured to emit second kind of light. The first light emitting device is stacked above the second light emitting device, or stacked below the second light emitting device. The present invention also discloses a dual wavelength light transceiving device which can transmit light and receive light by the same layer. Comparing with a conventional micro LED, the area occupied by the dual wavelength light emitting device or the dual wavelength light transceiving device can be reduced.

Abstract: An integrated circuit is attached to a chip carrier in a flip chip configuration. An electrically conductive conformal layer is disposed on a back surface of the substrate of the integrated circuit. The electrically conductive conformal layer contacts the semiconductor material in the substrate and extending onto, and contacting, a substrate lead of the chip carrier. The substrate lead of the chip carrier is electrically coupled to a substrate bond pad of the integrated circuit. The substrate bond pad is electrically coupled through an interconnect region of the integrated circuit to the substrate of the integrated circuit. A component is attached to the chip carrier and covered with an electrically insulating material. The electrically conductive conformal layer also extends at least partially over the electrically insulating material on the component. The electrically conductive conformal layer is electrically isolated from the component by the electrically insulating material on the component.

Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

Abstract: The present disclosure provides a white organic electroluminescent device, comprising: a substrate; an anode layer; a first light emitting layer formed from a red organic fluorescent material, a first energy-sensitized organic material and a first hole-type organic host material; a second light emitting layer formed from a green organic fluorescent material, a second energy-sensitized organic material and a second hole-type organic host material; and a cathode layer.

Abstract: Disclosed are systems and methods for a quantum-analogue computing bit array consisting of a single qubit analogue, a serial two qubit analogue coupling, or parallel N qubit analogues. The quantum-analogue computing bit array comprises an elastic media having photo-elastic and photo-expansion effects, the adjustment of which allows a manipulation of one or more structural degrees of freedom within the elastic media and one or more temporal degrees of freedom within the elastic media. At least one analogue qubit is defined by one or more elastic waves within the elastic media. The quantum-analogue computing bit array further comprises a modulated light source oriented to illuminate the elastic media with a laser radiation to achieve a non-separable multi-phonon superposition of states within the elastic media.

Abstract: A semiconductor device includes a trench extending into a first main surface of a semiconductor substrate, and a gate electrode and a gate dielectric in the trench. The gate dielectric separates the gate electrode from the semiconductor substrate. A first region having a first conductivity type is formed in the semiconductor substrate at the first surface adjacent the trench. A second region having a second conductivity type is formed in the semiconductor substrate below the first region adjacent the trench. A third region having the first conductivity type is formed in the semiconductor substrate below the second region adjacent the trench. A contact opening in the semiconductor substrate extends into the second region. An electrically insulative spacer is disposed on sidewalls of the semiconductor substrate formed by the contact opening, and an electrically conductive material in the contact opening adjoins the electrically insulative spacer on the sidewalls.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.

Abstract: There is disclosed a method (400) of operating a molding system (100), the method (400) executable by a controller (140) of the molding system (100). The method comprises appreciating (402) a plurality of operational parameters associated with the molding system (100); based on at least a sub-set of the plurality of operational parameters, generating (404) a machine performance index, the machine performance index being a single value representative of the at least a sub-set of the plurality of operational parameters and being instrumental in enabling an operator of the molding system (100) to appreciate an economic productivity factor associated therewith; causing (406) the machine performance index to be displayed on an interface of the controller (140).

Abstract: A wiring board includes an insulating substrate including a cutout portion that opens in a main surface of the insulating substrate and a side surface of the insulating substrate, an inner surface electrode on an inner surface of the cutout portion, an external electrode on the main surface of the insulating substrate, and a connecting section where the inner surface electrode and the external electrode are connected to each other. The connecting section is thicker than the inner surface electrode and the external electrode.

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.

Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

Abstract: A semiconductor apparatus includes a conductive member penetrating through a first semiconductor layer, a first insulator layer, and a third insulator layer, and connecting a first conductor layer with a second conductor layer. The conductive member has a first region containing copper, and a second region containing a material different from the copper is located at least between a first region and the first semiconductor layer, between the first region and the first insulator layer, and between the first region and the third insulator layer. A diffusion coefficient of the copper to a material is lower than a diffusion coefficient of the copper to the first semiconductor layer and a diffusion coefficient of the copper to the first insulator layer.

Abstract: A system for surgical planning and assessment of spinal deformity correction is provided that has a spinal imaging system and a control unit. The spinal imaging system is configured to collect at least one digitized position of one or more vertebral bodies of a subject. The control unit is configured to receive the at least one digitized position, and calculate, based on the at least one digitized position, an optimized posture for the subject. The control unit is configured to receive one or more simulated spinal correction inputs, and based on the inputs and optimized posture, predict an optimal simulated postoperative surgical correction.

Abstract: A method for forming a light-transmissive member includes irradiating a principal surface of a cured resin body containing a silicone resin with ultraviolet rays through a photomask comprising one or more light-blocking regions and one or more light-transmissive regions, so as to cause a height of one or more first regions of the principal surface, which correspond to the one or more light-blocking regions of the photomask, to be different than a height of one or more second regions of the principal surface, which correspond to the one or more light-transmissive regions of the photomask.

Abstract: A method of generating a layout diagram includes: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

Abstract: A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.

Abstract: An organic light-emitting display panel and a display device, comprising: multiple light-emitting components; pixel circuits connected one-to-one to the light-emitting components, the pixel circuits being connected to corresponding first poles of the light-emitting components, second poles of the light-emitting components being connected to first power ends; diversion modules corresponding one-to-one to the light-emitting components, wherein the diversion modules are connected at first ends thereof to the corresponding first poles of the light-emitting components and connected at second ends to the corresponding second poles of the light-emitting components, and the diversion modules are used for diversion with respect to the corresponding light-emitting components when the temperature of the organic light-emitting display panel satisfies a selected temperature range.