Abstract: Methods of processing a target material are disclosed. In one arrangement, a multilayer structure is irradiated with a radiation beam. The multilayer structure comprises at least a target layer comprising the target material and an additional layer not comprising the target material. The additional layer is metallic. The target layer is irradiated through the additional layer during the irradiation of the multilayer structure. A transfer of energy from the radiation beam to the target layer and to the additional layer is such as to cause a thermally-induced change in the target layer. The thermally-induced change comprising one or more of: crystal growth in the target material, increased carrier mobility in the target material, increased chemical stability in the target material, and increased uniformity of electrical properties in the target material.

Abstract: An array substrate includes a substrate, a dual-gate oxide thin film transistor TFT, an electrode for display and a polycrystalline silicon TFT. The dual-gate oxide thin film transistor TFT and the electrode for display are located in a sub-pixel on the substrate, and a drain electrode of the dual-gate oxide TFT is electrically connected to the electrode for display.

Abstract: Some embodiments include an integrated assembly which has a semiconductor material with a surface. A first layer is over and directly against the surface. The first layer includes oxygen and a first metal. The relative amount of oxygen to the first metal is less than or equal to an amount sufficient to form stoichiometric metal oxide throughout the first layer. A second metal is over and directly against the first layer. A second layer is over and directly against the second metal. The second layer includes nitrogen and a third metal. Some embodiments include an integrated assembly which has a semiconductor material with a surface. A metal is adjacent the surface and is spaced from the surface by a distance of less than or equal to about 10 ?. There is no metal germanide or metal silicide between the metal and the surface.

Abstract: A method for selectively depositing a metallic film on a substrate comprising a first dielectric surface and a second metallic surface is disclosed. The method may include, exposing the substrate to a passivating agent, performing a surface treatment on the second metallic surface, and selectively depositing the metallic film on the first dielectric surface relative to the second metallic surface. Semiconductor device structures including a metallic film selectively deposited by the methods of the disclosure are also disclosed.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure and at least one source structure extending vertically and laterally and dividing the stack structure into a plurality of block regions. The stack structure may include a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The at least one source structure includes at least one support structure extending along the vertical direction to the substrate, the at least one support structure being in contact with at least a sidewall of the respective source structure.

Abstract: The present application discloses a method of fabricating an array substrate. The method includes forming a first conductive material layer on a base substrate; forming an insulating layer on a side of the first conductive material layer distal to the base substrate, the insulating layer formed to cover a first part of the first conductive material layer, exposing a second part of the first conductive material layer; over-etching the first conductive material layer to remove the second part of the first conductive material layer, and remove a portion of a periphery of the first part of the first conductive material layer to form a recess between the insulating layer and the base substrate, thereby forming a first electrode; and subsequent to forming the first electrode and the recess, annealing the insulating layer to mobilize a portion of the insulating layer above the recess and fill the recess with a mobilized insulating material.

Abstract: A semiconductor device includes a substrate, a first semiconductor auxiliary film, a semiconductor film, a gate insulating film, and a gate electrode. The first semiconductor auxiliary film is provided in a selective region on the substrate. The semiconductor film includes an oxide semiconductor material, and has a low-resistive region in contact with the first semiconductor auxiliary film and a channel region provided in a portion different from the low-resistive region. The gate insulating film covers the semiconductor film from the channel region to at least part of the low-resistive region. The gate electrode is opposed to the channel region of the semiconductor film via the gate insulating film.

Abstract: A light-emitting device assembly includes a light-emitting device including a light-emitting layer, a first electrode, and a second electrode, and a first connecting portion and a second connecting portion provided on a base, in which the first connecting portion and the second connecting portion are separated from each other by a separation portion, the base is exposed from the separation portion, a wide portion is on a first connecting portion side of the separation portion, the first electrode includes a first portion and a second portion, the second portion of the first electrode is connected to the first connecting portion, the first portion of the first electrode extends from the second portion of the first electrode, and an orthographic projection image of the first portion of the first electrode with respect to the base and the wide portion of the separation portion overlap with each other at least in part.

Abstract: A redistribution substrate includes a first conductive pattern including a first lower pad and a second lower pad, the first and second lower pads being within a first insulating layer, a second conductive pattern including a first upper pad and a second upper pad, the first and second upper pads being on the first insulating layer, a first via connecting the first lower pad and the first upper pad to each other in the first insulating layer, a second via connecting the second lower pad and the second upper pad to each other in the first insulating layer, and a capacitor between the first lower pad and the first via.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided, which pertain to the field of display technologies. The display substrate includes a display area and a package area surrounding the display area. The display substrate includes a base substrate and an interlayer insulating layer on the substrate. The interlayer insulating layer has a groove, an orthographic projection of the groove on the base substrate is located within an orthographic projection of the package area on the base substrate, and the groove is provided with a sealing material.

Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.

Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.

Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.

Abstract: Disclosed is an optical component package. The optical component package according to the present invention includes: a main substrate including a plurality of metal bodies, and a vertical insulation part provided between the metal bodies; a sub-substrate provided in a cavity of the main substrate, and electrically connected to each of the metal bodies with the vertical insulation part interposed therebetween; an optical component mounted on the sub-substrate; and a light transmitting member provided above the optical component, wherein the sub-substrate includes: an insulating body; a via hole vertically passing through the insulating body, and filled with a metal material; and a metal pad connected to the optical component.

Abstract: In a chip, a manufacturing method, and a mobile terminal, the chip includes a first region and a second region. The first region is formed by at least one first circuit unit set. The second region is formed by a second circuit unit set. The at least one first circuit unit set includes a plurality of identical circuit units. A number of circuit units in the first region determines a specification of the chip and a size of the first region of the chip.

Abstract: The invention discloses a NOR-type memory device and a method of fabricating such NOR-type memory device. The NOR-type memory device according to a preferred embodiment of the invention includes a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of multi-layer stripes, a plurality of memory cells, a plurality of first sub-bit lines, a plurality of second sub-bit line, a plurality of word lines, an insulating layer, a plurality of grounded via contacts, and a grounding layer. The first isolation stripes and the second isolation stripes extend in a longitudinal direction defined by the semiconductor substrate. Each memory cell corresponds to one of the columns and one of the rows defined by the semiconductor substrate. The memory cells on one side of each first isolation stripe and the memory cells on the other side of said one first isolation stripe are staggeredly arranged.

Abstract: A method of fabricating an array substrate, an array substrate, and a display device is disclosed. The array substrate comprises a display area and a wiring area. The display area is disposed with a first thin film transistor and a second thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor comprises first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove comprises a first sub-groove and a second sub-groove that are stacked. The method includes simultaneously forming the first vias and the first sub-groove, and simultaneously forming the second vias and the second sub-groove.

Abstract: Provided is a crystalline multilayer structure having good semiconductor properties. The crystalline multilayer structure includes a base substrate and a corundum-structured crystalline oxide semiconductor thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide semiconductor thin film is 0.1 ?m or less in a surface roughness (Ra).

Abstract: A spin-transfer torque (STT) magnetoresistive memory device includes a first electrode, a second electrode, and a magnetic tunnel junction located between the first electrode and the second electrode. The magnetic tunnel junpction includes a reference layer having a fixed magnetization direction, a free layer stack, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer stack. The free layer stack has a total thickness of less than 2 nm, and contains in order, a proximal ferromagnetic layer located proximal to the nonmagnetic tunnel barrier layer, a first non-magnetic metal sub-monolayer, an intermediate ferromagnetic layer, a second non-magnetic metal sub-monolayer, and a distal ferromagnetic layer.

Abstract: The present disclosure provides a transistor, an array substrate and a method of manufacturing the array substrate, and a display device. The method of manufacturing the array substrate comprises: depositing a plurality of silicon oxide layers on an active layer of a transistor; and depositing a silicon oxynitride layer over the plurality of silicon oxide layers.