Abstract: A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the first active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

Abstract: A method for forming a salicide includes forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape, forming a conductive material on the (111) facet, annealing the conductive material to form a silicide on the (111) facet, and forming at least one contact to the silicide.

Abstract: A method of manufacturing a semiconductor device comprises forming an integrated circuit, surrounding the integrated circuit with an inner seal ring, and surrounding the inner seal ring with a closed-loop outer seal ring. The inner seal ring includes a plurality of metal layers in a stacked configuration, first and second seal portions separated from each other, and third and fourth seal portions spaced apart from the first and second seal portions and separated from each other.

Abstract: Disclosed are a thin film transistor (TFT) including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving, a gate driver including the TFT, and a display device including the gate driver. The TFT includes first oxide semiconductor layer consisting of indium-gallium-zinc-tin oxide (IGZTO) and a second oxide semiconductor layer including indium-gallium-zinc oxide (IGZO). A content ratio (Ga/In) of gallium (Ga) to indium (In) of the second oxide semiconductor layer is higher than a content (Ga/In) of Ga to In of the first oxide semiconductor layer, and a content ratio (Zn/In) of zinc (Zn) to In of the second oxide semiconductor layer is higher than a content (Zn/In) of Zn to In of the first oxide semiconductor layer.

Abstract: A method for producing a nitride fluorescent material having high emission luminance can be provided. The method includes heat-treating a raw material mixture containing silicon nitride, silicon, an aluminium compound, a calcium compound, and a europium compound.

Abstract: An optoelectronic device including a substrate including first and second opposite surfaces and lateral electrical insulation elements extending in the substrate and delimiting first electrically-insulated semiconductor or conductive portions. The optoelectronic device includes, for each first portion, an assembly of light-emitting diodes electrically coupled to the first portion. The optoelectronic device includes an electrode layer covering all the light-emitting diodes, a protection layer covering the electrode layer, and walls extending in the protection layer and delimiting second portions surrounding or opposite the assemblies of light-emitting diodes. The walls contain at least one material from the group including air, a metal, a semiconductor material, a metal alloy, a partially transparent material, and a core made of an at least partially transparent material covered with an opaque or reflective layer.

Abstract: A method for reducing warpage occurred to a substrate strip after a molding process is provided. First, several dies are mounted on a top surface of a substrate strip. Then, a base having a top surface with a surface curvature is provided, and the top surface of the base is contacted against a bottom surface of the substrate strip to bend the substrate strip. Next, under the status that the top surface of the base is contacted against the bottom surface of the substrate strip, a molding compound is wrapped around each die. Finally, the molding compound is cooled to a room temperature. Accordingly, the molding process is performed on the substrate strip reversely bent in a direction opposite to a warpage direction. Therefore, the warpage originally caused by the molding process is offset by the reverse bending.

Abstract: An upper layer (4,5) made of non-doped III-V compound semiconductor is formed on a lower layer (3) made of non-doped III-V compound semiconductor. Impurity source gas is fed through vapor phase diffusion using an organometallic vapor-phase epitaxy device to add an impurity to the upper layer (4,5). The vapor phase diffusion is continued with the feed of the impurity source gas stopped or with a feed amount of the impurity source gas lowered.

Abstract: The present invention relates to formulations for the preparation of organic electronic devices which comprise at least one specific A/JV-dialkylaniline and at least one organic functional material selected from organic conductors, organic semiconductors, organic fluorescent compounds, organic phosphorescent compounds, organic light-absorbent compounds, organic light-sensitive compounds, organic photosensitisation agents and other organic photoactive compounds, selected from organometallic complexes of transition metals, rare earths, lanthanides and actinides.

Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.

Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a carboxylic acid is exposed to a substrate to selectively form a blocking layer. In some embodiments, a hydrazide is exposed to a substrate to selectively form a blocking layer. In some embodiments, an alkyl phosphonic acid is exposed to a substrate to selectively form a blocking layer. In some embodiments, the alkyl phosphonic acid is formed in-situ and exposed to the substrate. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed.

Abstract: Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.

Abstract: A method of forming a tungsten film having low resistance is provided. The method includes forming a discontinuous film containing a metal on a substrate; and forming the tungsten film on the substrate on which the discontinuous film is formed. In the forming of the discontinuous film, a first source gas and a nitriding gas are supplied onto the substrate alternately along with, for example, a carrier gas. In the forming of the tungsten film, a second source gas and a reducing gas are supplied onto the substrate alternately along with, for example, a carrier gas.

Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

Abstract: Disclosed herein is a method for fabricating a flexible colloidal crystal heterostructure. The method may include applying cold plasma treatment on a top surface of a flexible polymer substrate, horizontally depositing monodispersed polystyrene colloidal particles onto the top surface of the flexible polymer substrate, and creating a vertical temperature gradient in layers of monodispersed polystyrene colloidal particles. The vertical temperature gradient may be perpendicular to the top surface and may be created by heating an opposing bottom surface of the flexible polymer substrate.

Abstract: A light-emitting device includes a flip-chip LED semiconductor chip to provide a primary light, a photoluminescent (PL) structure disposed on the LED semiconductor chip and a moisture-barrier reflective structure covering a chip-edge surface of the LED semiconductor chip and a photoluminescent-side surface of the PL structure. The sequentially stacked PL structure includes a first PL layer, a transparent isolation layer, a second PL layer and a transparent moisture barrier layer. For example, the LED semiconductor chip emits a blue light, the first PL layer includes a red phosphor material, and the second PL layer includes a green quantum dot (QD) material. Therefore, the red phosphor material of the first PL layer can convert a portion of the higher-energy-level blue light into a lower-energy-level converted red light, so as to reduce an intensity of an unconverted portion of the blue light reaching the green QD material within the second PL layer.

Abstract: Methods, systems, and devices for enabling the use of a special, generic, or standard substrate for similar system SIP assemblies are disclosed. The required customization, which is defined by a system's interconnecting scheme, is done during package assembly by creating appropriate connections using wire bonds on pads that are placed on the substrate and intentionally left open for purpose of customization. The wire bond links can be changed as required for a given system design.

Abstract: A method for the surface treatment of a substrate surface of a substrate includes arranging the substrate surface in a process chamber, bombarding the substrate surface with an ion beam, generated by an ion beam source and aimed at the substrate surface, to remove impurities from the substrate surface, whereby the ion beam has a first component, and introducing a second component into the process chamber to bind the removed impurities. A device for the surface treatment of a substrate surface of a substrate includes a process chamber for receiving the substrate, an ion beam source for generating an ion beam that has a first component and is aimed at the substrate surface to remove impurities from the substrate surface, and means to introduce a second component into the process chamber to bind the removed impurities.

Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.

Abstract: An array substrate for a liquid crystal display device can include a plurality of gate lines arranged in one direction to correspond to an active area on a substrate; a plurality of data lines configured to cross the plurality of gate lines in a perpendicular direction; a plurality of pixel electrodes respectively positioned at intersections between the plurality of gate lines and the plurality of data lines; and a plurality of data link lines respectively connected to a (4n?2)th data line in the active area and a (4n?2)th data pad in the non-active area, and a (4n?1)th data line in the active area and a (4n?1)th data pad in the non-active area, where n is a natural number, in which at least some of the plurality of data link lines are located at a different layer level than the plurality of data lines.