Abstract: A display device is provided, including a display panel; a light-emitting element disposed under the display panel; an optical functional film disposed between the display panel and the light-emitting element. The optical functional film is capable of transmitting at least part of the light emitted from the light-emitting element. A diffuser film is disposed between the display panel and the light-emitting element. The haze of the diffuser film is greater than 85%, and the thickness of the diffuser film ranges from 0.1 mm to 0.3 mm.

Abstract: Systems and methods for forming semiconductor layers, including oxide-based layers, are disclosed in which a material deposition system has a rotation mechanism that rotates a substrate around a center axis of a substrate deposition plane of the substrate. A material source that supplies a material to the substrate has i) an exit aperture with an exit aperture plane and ii) a predetermined material ejection spatial distribution from the exit aperture plane. The exit aperture is positioned at an orthogonal distance, a lateral distance, and a tilt angle relative to the center axis of the substrate. The system can be configured for either i) minimum values for the orthogonal distance and the lateral distance to achieve a desired layer deposition uniformity using a set tilt angle, or ii) the tilt angle to achieve the desired layer deposition uniformity using a set orthogonal distance and a set lateral distance.

Abstract: An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.

Abstract: The light emitting device includes: a light emitting element, a covering member, a pair of electrode layers, and a pair of electrode terminals. The light emitting element has an electrode-formed surface on which a pair of electrode posts are formed. The covering member covers an electrode-formed surface of the light emitting element while forming an exposed portion of each of the pair of electrode posts which is exposed from the covering member. The pair of electrode layers are provided on a surface of the covering member and electrically connected to the exposed portions of the pair of electrode posts. The pair of electrode terminals are electrically connected to the pair of electrode layers, and provided on the surface of the covering member. The pair of electrode terminals are thicker than the pair of electrode layers, and are disposed at an interval larger than an interval between the pair of electrode posts.

Abstract: A circuit backplane of a display panel, a method for manufacturing the same, and a display panel are provided. The circuit backplane includes a substrate and a plurality of circuit regions on the substrate. Each of the plurality of circuit regions includes a cathode soldered electrode, an anode soldered electrode, and a flow blocking island that are on the substrate. The flow blocking island is between the cathode soldered electrode and the anode soldered electrode, and in a thickness direction of the circuit backplane, a height of the flow blocking island is greater than each of a height of the cathode soldered electrode and a height of the anode soldered electrode.

Abstract: A semiconductor device includes a semiconductor fin, a gate cut region, a first gate structure and a second gate structure. The semiconductor fin extends from a substrate. The gate cut region extends in parallel with a longitudinal axis of the semiconductor fin and not overlaps the semiconductor fin. The first gate structure and the second gate structure extend across the semiconductor fin. The first gate structure is laterally between the gate cut region and the second gate structure along a direction parallel with the longitudinal axis of the semiconductor fin. The first gate structure has a greater width variation than the second gate structure.

Abstract: The present invention discloses a display panel and a display device. By adding a stress adjustment layer having a plurality of patterned structures spaced apart from each other, the stress neutral surface can be effectively adjusted, and the stress of the metal trace is reduced when it is bent, to avoid or mitigate excessive stress causing generation and expansion of cracks in the stress adjustment layer, thereby reducing the probability of breakage of the metal trace when the flexible display is bent, thus reducing the risk of failure of the metal trace.

Abstract: Methods for depositing a metal film on a doped amorphous silicon layer as a nucleation layer and/or a glue layer on a substrate. Some embodiments further comprise the incorporation of a glue layer to increase the ability of the doped amorphous silicon layer and metal layer to stick to the substrate.

Abstract: Provided is a method of producing an epitaxial silicon wafer having high gettering capability resulting in even more reduced white spot defects in a back-illuminated solid-state imaging device. The method includes: a first step of irradiating a surface of a silicon wafer with cluster ions of CnHm (n=1 or 2, m=1, 2, 3, 4, or 5) generated using a Bernas ion source or an IHC ion source, thereby forming, in the silicon wafer, a modifying layer containing, as a solid solution, carbon and hydrogen that are constituent elements of the cluster ions; and a subsequent second step of forming a silicon epitaxial layer on the surface. In the first step, peaks of concentration profiles of carbon and hydrogen in the depth direction of the modifying layer are made to lie in a range of more than 150 nm and 2000 nm or less from the surface.

Abstract: A light-emitting device and a method for manufacturing a light-emitting device are disclosed. In an embodiment a light-emitting device includes a light-emitting semiconductor chip with a light-outcoupling surface surrounded laterally by a first reflective material in a form-locking manner, a foil element on the light-outcoupling surface, an optical element on the foil element laterally surrounded by a second reflective material in a form-locking manner and a gas-filled gap located at least in a partial region between the foil element and the optical element.

Abstract: An integrated circuit (IC) package incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate having an active side upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers may be deposited to the opposing, or inactive, side of the semiconducting die via electroplating in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree.

Abstract: An integrated circuit (IC) package incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate having an active side upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers may be deposited to the opposing, or inactive, side of the semiconducting die via thin film deposition (TFD) instrumentation and techniques in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree.

Abstract: The present disclosure provides a substrate, a manufacturing method thereof, and a transparent display device. The substrate comprising: a plurality of pixel units, at least a part of which includes a light-emitting area and a transparent area, and the light-emitting area includes a thin-film transistor; a light blocking member disposed in the light-emitting area and configured to block light that is directed to the thin-film transistor through the transparent area.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes an N-type doped region of a substrate, an N-type doped semiconductor layer on the N-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the N-type doped region, and a source contact structure extending vertically through the memory stack and the N-type doped semiconductor layer into the N-type doped region. A first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the memory stack.

Abstract: Device package and method of forming a device package are described. The device package has a substrate with dies disposed on the substrate. Each die has a bottom surface that is electrically coupled to the substrate and a top surface. The device package further includes a plurality of stiffeners disposed directly on the substrate. The stiffeners may be directly attached to a top surface of the substrate without an adhesive layer. The device package may include stiffeners with one or more different sizes and shapes, including at least one of a rectangular stiffener, a picture frame stiffener, a L-shaped stiffener, a H-shaped stiffener, and a round pillar stiffener. The device package may have the stiffeners disposed on the top surface of the substrate using a cold spray process. The device package may also include a mold layer formed around and over the dies, the stiffeners, and the substrate.

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

Abstract: A method includes forming a light-sensitive element in a substrate. The substrate is doped with a first dopant to form a pinning region over a first portion of the light-sensitive element. A second portion of the light-sensitive element is surrounded by the pinning region. A first contact is formed in contact with the second portion of the light-sensitive element, and a second contact is formed over the pinning region.

Abstract: The present application discloses an array substrate having a plurality of thin film transistors, a display apparatus, and a method of fabricating an array substrate. The array substrate includes a base substrate; a semiconductor layer on the base substrate and including a plurality of active layers respectively for the plurality of thin film transistors; and an electrostatic discharging layer electrically connected to the semiconductor layer and configured to discharge electrostatic charge in the semiconductor layer.

Abstract: An ion implantation method includes changing an ion acceleration energy and/or an ion beam current density of an ion beam while effecting a relative movement between a semiconductor substrate and the ion beam impinging on a surface of the semiconductor substrate.

Abstract: Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer.