Patents Examined by Bo B Jang
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Patent number: 11195970Abstract: An LED panel including a substrate, multiple first pixels, multiple second pixels, multiple first protrusion structures and second protrusion structures is provided. The first pixels and second pixels each disposed in a display area of the substrate has at least one light emitting element. The second pixels are positioned on at least one display edge of the display area and positioned between the first pixels and a substrate edge. Each first protrusion structure is positioned on the periphery of the at least one light emitting element of one corresponding first pixel. Each second protrusion structure is positioned on the periphery of the at least one light emitting element of one corresponding second pixel. The orthogonal projection contour of each first protrusion structure on the substrate is different from that of each second protrusion structure on the substrate. A tiling display apparatus adopting the light emitting diode panel is also provided.Type: GrantFiled: November 18, 2019Date of Patent: December 7, 2021Assignee: Au Optronics CorporationInventors: Fang-Cheng Yu, Wen-Wei Yang, Pin-Miao Liu
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Patent number: 11189761Abstract: An image display device includes a plurality of pixels each of which includes a plurality of first subpixels and a second subpixel. The plurality of first subpixels is configured to emit red light, green light, and blue light. The second subpixel is configured to emit blue light. The plurality of pixels includes at least one pixel in which the plurality of first subpixels includes a defective subpixel which is supposed to emit predetermined light with a predetermined color. The second subpixel includes a light-emitting element and a wavelength conversion layer provided over the light-emitting element to convert emission light emitted from the light-emitting element to converted light with the predetermined color if the predetermined color is red or green.Type: GrantFiled: December 26, 2019Date of Patent: November 30, 2021Assignee: NICHIA CORPORATIONInventor: Hajime Akimoto
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Patent number: 11189577Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate. The semiconductor structure also includes a buffer layer disposed on the substrate. The semiconductor structure further includes a first semiconductor layer disposed on the buffer layer. The buffer layer includes a first buffer structure and a second buffer structure partially disposed on the first buffer structure. The material of the first buffer structure is different from the material of the second buffer structure.Type: GrantFiled: April 6, 2020Date of Patent: November 30, 2021Assignee: PLAYNITRIDE DISPLAY CO., LTD.Inventors: Hsin-Chiao Fang, Shen-Jie Wang, Yen-Lin Lai
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Patent number: 11183618Abstract: A light emission element includes a first semiconductor layer, a light emission layer, and a second semiconductor layer. The first semiconductor layer in the light emission portion is provided with a concave portion having a concave shape. The light emission layer and the second semiconductor layer disposed on the first semiconductor layer are also disposed along the concave shape of the concave portion. The light emitting layer disposed along the shape of the concave portion emits light by electrons and holes injected from the first semiconductor layer and the second semiconductor layer. Further, the light path of the light emitted according to the concave shape is adjusted. Therefore, a light emission element having improved light efficiency and a display device using the same can be provided.Type: GrantFiled: December 23, 2019Date of Patent: November 23, 2021Assignee: LG DISPLAY CO., LTD.Inventors: Junghun Choi, SeungJun Lee, MinJoo Kim, KyuOh Kwon
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Patent number: 11183532Abstract: A device includes a substrate, a light sensitive element, a pinning region, a lightly-doped region, a floating node, and a gate stack. The light sensitive element is in the substrate. The pinning region is in the substrate and is over the light sensitive element. The lightly-doped region is in the pinning region. The floating node is in the pinning region. The floating node is spaced from and is surrounded by the lightly-doped region. A first portion of the pinning region between the floating node and the lightly-doped region forms a channel region. A gate stack is over the channel region.Type: GrantFiled: November 25, 2019Date of Patent: November 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Bo-Tsung Tsai
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Patent number: 11177209Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.Type: GrantFiled: November 21, 2019Date of Patent: November 16, 2021Assignee: SK hynix Inc.Inventors: Jin Won Lee, Nam Jae Lee
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Patent number: 11177419Abstract: An optical device includes two substrates disposed opposite to each other. Each of the substrates has a surrounding edge and a side surface at the surrounding edge. A wavelength conversion layer is disposed between the two substrates. A light emitting unit corresponding to the wavelength conversion layer is disposed between the corresponding wavelength conversion layer and one of the two substrates. A sealing element is disposed along the edges and in contact with the side surfaces of the two substrates, and seals the wavelength conversion layer and the light emitting unit located between the two substrates.Type: GrantFiled: May 20, 2020Date of Patent: November 16, 2021Assignee: Innolux CorporationInventors: Shu-Ming Kuo, Tsau-Hua Hsieh
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Patent number: 11171000Abstract: A laser crystallization system includes a transfer part that transfers a substrate on which an amorphous silicon thin film is deposited into a chamber, a laser irradiation part that irradiates an excimer laser to the substrate for crystallization of the amorphous silicon thin film in the chamber, a stage that supports the substrate in the chamber, a measuring part that measures a light transmittance value of the substrate, and a controller that controls the laser irradiation part to irradiate the excimer laser to the substrate when the light transmittance value is equal to or lower than a reference transmittance value and controls the laser irradiation part not to irradiate the excimer laser to the substrate when the light transmittance value is higher than the reference transmittance value.Type: GrantFiled: May 1, 2020Date of Patent: November 9, 2021Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jongoh Seo, Jonghoon Choi, Ji-Hwan Kim, Byung Soo So, Dong-Min Lee, Dong-Sung Lee
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Patent number: 11164742Abstract: Processes for selective deposition of material on a workpiece are provided. In one example, the method includes placing a workpiece on a workpiece support in a processing chamber. The workpiece has a first material and a second material. The second material is different from the first material. The method includes performing an organic radical based surface treatment process on the workpiece to modify an adsorption characteristic of the first material selectively relative to the second material such that the first material has a first adsorption characteristic and the second material has a second adsorption characteristic. The second adsorption characteristic being different from the first adsorption characteristic. The method includes performing a deposition process on the workpiece such that a material is selectively deposited on the first material relative to the second material.Type: GrantFiled: April 29, 2020Date of Patent: November 2, 2021Assignees: Beijing E-Town Semiconductor Technology Co., Ltd., Mattson Technology, Inc.Inventors: Michael X. Yang, Hua Chung, Xinliang Lu
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Patent number: 11158504Abstract: A method of making polycrystalline silicon (p-Si), including: depositing amorphous silicon to produce an amorphous silicon super-mesa; dehydrogenating the amorphous silicon; patterning the super-mesa to produce a patterned substrate; depositing a capping oxide layer on the amorphous silicon on the patterned substrate; heating the capped, patterned substrate to the crystallization temperature of the a-Si; and flash lamp annealing the patterned substrate with a xenon lamp to produce p-Si having at least one super-mesa, and the super-mesa having supersized grains. Also disclosed are p-Si articles and devices incorporating the articles, and an apparatus for making the p-Si articles.Type: GrantFiled: July 30, 2018Date of Patent: October 26, 2021Assignee: Corning IncorporatedInventors: Karl D Hirschman, Robert George Manley, Tarun Mudgal
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Patent number: 11145606Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.Type: GrantFiled: March 26, 2020Date of Patent: October 12, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed A. Rabie, Andreas D. Stricker
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Patent number: 11145561Abstract: The present disclosure provides a display panel and a method for manufacturing the same. The method includes providing a substrate including a display area and a non-display area. A chip on film (COF) and a testing structure are disposed in the non-display area. A testing circuit includes a signal trace including a non-metal trace and a metal trace connecting to each other. A cutting line is disposed on the signal trace. The method further includes testing the display area of the substrate by the testing structure, and removing a test pad.Type: GrantFiled: April 18, 2019Date of Patent: October 12, 2021Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventors: Xing Ming, Caiqin Chen, Yiyi Wang
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Patent number: 11126048Abstract: An array substrate includes gate lines, data lines, and pixel units defined by adjacent gate lines and adjacent data lines, the gate lines, the data lines, and the pixel units being formed on a substrate, wherein the gate line gradually becomes wider from a driving start end to a driving terminal end. on the array substrate.Type: GrantFiled: September 22, 2017Date of Patent: September 21, 2021Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Hao Chu, Yue Shi, Chuanbao Chen
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Patent number: 11121287Abstract: A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a carrier having a pedestal with a support surface, applying a liquid joining material with filler particles to the support surface of the pedestal and applying a radiation emitting semiconductor chip with a mounting surface, which is larger than the support surface of the pedestal to the liquid joining material such that the joining material forms a joining layer between the support surface of the pedestal and the mounting surface of the semiconductor chip and the joining material at least partially fills only a recess, which is limited by a part of the mounting surface projecting beyond the support surface.Type: GrantFiled: July 9, 2018Date of Patent: September 14, 2021Assignee: OSRAM OLED GMBHInventor: Ivar Tangring
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Patent number: 11114570Abstract: A memory structure includes a substrate, a gate electrode, a first isolation layer, a thin metal layer, indium gallium zinc oxide (IGZO) particles, a second isolation layer, an IGZO channel layer, and a source/drain electrode. The gate electrode is located on the substrate. The first isolation layer is located on the gate electrode. The thin metal layer is located on the first isolation layer, and has metal particles. The IGZO particles are located on the metal particles. The second isolation layer is located on the IGZO particles. The IGZO channel layer is located on the second isolation layer. The source/drain electrode is located on the IGZO channel layer.Type: GrantFiled: April 12, 2020Date of Patent: September 7, 2021Assignee: E Ink Holdings Inc.Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Ching-Fu Lin, Zong-Xuan Li, Wei-Tsung Chen
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Patent number: 11114541Abstract: Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.Type: GrantFiled: September 28, 2020Date of Patent: September 7, 2021Inventors: Sunmin Moon, Young-Lim Park, Kyuho Cho, Hanjin Lim
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Patent number: 11114514Abstract: An organic electroluminescent display panel is provided, including a pixel defining layer. The pixel defining layer includes a plurality of openings and a bank surrounding each of the plurality of openings and defining a plurality of pixel areas. The bank is composed of a hydrophilic material pattern layer and a conductive hydrophobic pattern layer which are stacked from bottom to top.Type: GrantFiled: March 12, 2019Date of Patent: September 7, 2021Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Kui Gong, Xianxue Duan, Zhihai Zhang
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Patent number: 11114473Abstract: A method for transferring light emitting elements precisely during manufacture of display panels includes providing light emitting elements; providing a first electromagnetic plate defining magnetic adsorption positions; providing a receiving substrate defining receiving areas; providing a second electromagnetic plate; energizing the first electromagnetic plate to magnetically adsorb one light emitting element at one adsorption position; providing a second electromagnetic plate; and transferring the light emitting elements to one receiving area of the receiving substrate.Type: GrantFiled: November 13, 2019Date of Patent: September 7, 2021Assignee: Century Technology (Shenzhen) Corporation LimitedInventors: Po-Liang Chen, Yung-Fu Lin
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Patent number: 11107679Abstract: Methods of processing a target material are disclosed. In one arrangement, a multilayer structure is irradiated with a radiation beam. The multilayer structure comprises at least a target layer comprising the target material and an additional layer not comprising the target material. The additional layer is metallic. The target layer is irradiated through the additional layer during the irradiation of the multilayer structure. A transfer of energy from the radiation beam to the target layer and to the additional layer is such as to cause a thermally-induced change in the target layer. The thermally-induced change comprising one or more of: crystal growth in the target material, increased carrier mobility in the target material, increased chemical stability in the target material, and increased uniformity of electrical properties in the target material.Type: GrantFiled: February 5, 2020Date of Patent: August 31, 2021Assignee: National University of Ireland, GalwayInventors: Gerard O'Connor, Nazar Farid, Pinaki Das Gupta
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Patent number: 11107843Abstract: An array substrate includes a substrate, a dual-gate oxide thin film transistor TFT, an electrode for display and a polycrystalline silicon TFT. The dual-gate oxide thin film transistor TFT and the electrode for display are located in a sub-pixel on the substrate, and a drain electrode of the dual-gate oxide TFT is electrically connected to the electrode for display.Type: GrantFiled: October 9, 2017Date of Patent: August 31, 2021Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Lianjie Qu, Bingqiang Gui, Yonglian Qi, Hebin Zhao, Yun Qiu, Dan Wang