Patents Examined by Bo B Jang
  • Patent number: 10381430
    Abstract: A structure with an interconnection layer for redistribution of electrical connections includes a plurality of first electrical connections disposed on a substrate in a first arrangement. An insulating layer is disposed on the substrate over the first electrical connections. A plurality of second electrical connections is disposed on the insulating layer on a side of the insulating layer opposite the plurality of first electrical connections in a second arrangement. Each second electrical connection is electrically connected to a respective first electrical connection. An integrated circuit is disposed on the substrate and is electrically connected to the first electrical connections. The first electrical connections in the first arrangement have a greater spatial density than the second electrical connections in the second arrangement.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 13, 2019
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Matthew Meitl, Ronald S. Cok
  • Patent number: 10381291
    Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Brandon M. Rawlings, Aleksandar Aleksov, Feras Eid, Javier Soto
  • Patent number: 10373827
    Abstract: A method of pattern transfer is provided, comprising: providing a target layer; forming a first pattern above the target layer; forming a second pattern (such as spacer loops) above the target layer and above the first pattern, wherein one closed end of the second pattern partially overlaps with the first pattern; and transferring the second pattern to the target layer, wherein the first pattern stops transferring pattern of the closed end of the second pattern to the target layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10373879
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure over a substrate, forming gate spacers over the substrate, cutting the first dummy gate structure to form separated dummy gate portions, forming a dielectric feature between the dummy gate portions, and performing a thermal process to the dielectric feature to contract the dielectric feature, wherein the contraction of the dielectric feature deforms at least one of the gate spacers such that a distance between the gate spacers is increased.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon-Jhy Liaw
  • Patent number: 10366956
    Abstract: A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen, Ho-Chun Liou
  • Patent number: 10364314
    Abstract: A compound or a resin represented by the following formula (1).
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 30, 2019
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kana Okada, Junya Horiuchi, Takashi Makinoshima, Masatoshi Echigo
  • Patent number: 10359701
    Abstract: A material for forming an underlayer film for lithography, in which a compound represented by the following formula (0) is used.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: July 23, 2019
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kana Okada, Takashi Makinoshima, Masatoshi Echigo, Go Higashihara, Atsushi Okoshi
  • Patent number: 10325933
    Abstract: The present disclosure provides an array substrate comprising a plurality of gate lines, and a plurality of data lines that intersect the plurality of gate lines. A plurality of pixel units are defined by the plurality of gate lines and the plurality of data lines which intersect each other. Each pixel unit comprises a thin film transistor, a gate insulating layer, a passivation layer arranged on one side of the gate insulating layer, a pixel electrode and a common electrode, wherein a source and a drain of the thin film transistor are arranged between the passivation layer and the gate insulating layer, the common electrode is arranged on the other side of the gate insulating layer opposite to the passivation layer, and the pixel electrode is arranged on the passivation layer. The present disclosure further provides a method for manufacturing an array substrate and a display device.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 18, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yunyun Tian, Hyunsic Choi, Yoonsung Um
  • Patent number: 10325928
    Abstract: Provided are a method of manufacturing a thin film transistor, a dehydrogenating apparatus for performing the method, and an organic light emitting display device including a thin film transistor manufactured by the same. A method of manufacturing a thin film transistor includes reducing a content of oxygen in a chamber for performing a dehydrogenation process of an amorphous silicon layer from a first value to a second value, inserting a substrate on which the amorphous silicon layer is formed into the chamber, heating the inside of the chamber to perform the dehydrogenation process on the amorphous silicon layer, and forming a polysilicon layer by crystallizing the amorphous silicon layer using a laser.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 18, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Sung soo Lee
  • Patent number: 10325920
    Abstract: A method for manufacturing a semiconductor device includes forming a first mask layer having a first opening on an underlying layer; forming a first layer in a space where the underlying layer is selectively removed via the first opening; forming a second mask layer on the first mask layer and the first layer, the second mask layer having a second opening crossing the first opening; and selectively removing the first layer at a portion where the first opening and the second opening cross. At least one of the first and second mask layers having openings including the first or second opening, the openings being arranged in the first mask layer along a first direction, and/or being arranged in the second mask layer along a second direction, the first opening crossing the second opening in the first direction, and the second opening crossing the first opening in the second direction.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chihiro Abe, Keisuke Kikutani, Katsumi Yamamoto, Tomoya Oori
  • Patent number: 10262930
    Abstract: An interposer includes an insulating layer, conductor circuits formed in grooves formed on a first surface of the insulating layer respectively, and metal posts formed in openings extending from the grooves to a second surface of the insulating layer on the opposite side with respect to the first surface such that the metal posts are connected to the conductor circuits respectively. The insulating layer has an opening portion which accommodates an electronic component and is extending from the first surface to the second surface of the insulating layer, and each of the metal posts has an upper surface and a bottom surface on the opposite side of the upper surface such that the upper surface is connected to a respective one of the conductor circuits and that the bottom surface is exposed from the second surface of the insulating layer.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 16, 2019
    Assignee: IBIDEN CO., LTD.
    Inventor: Kazuki Kajihara
  • Patent number: 10256225
    Abstract: A gate-less electrostatic discharge (ESD) protection device is provided that can be formed in various complementary metal-oxide-semiconductor (CMOS) systems. The gate-less ESD event protection device includes a substrate, a first doped region formed in the substrate, a second doped region extending into the first doped region, a third doped region extending into the first doped region, a first node formed over a portion of the second doped region and coupled to a source terminal and a second node formed over the third doped region and coupled to a drain terminal. The gate-less ESD protection devices can be formed such that no gate electrode is formed and the gate-less ESD protection device does not include a gate terminal. Thus, an operating voltage range of the gate-less ESD protection device is not limited by gate oxide degradation.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 9, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Maxim Klebanov, Washington Lamar
  • Patent number: 10256163
    Abstract: Embodiments of the invention provide a method for treating a microelectronic substrate with dilute TMAH. In the method, a microelectronic substrate is received into a process chamber, the microelectronic substrate having a layer, feature or structure of silicon. A treatment solution is applied to the microelectronic substrate to etch the silicon, where the treatment solution includes a dilution solution and TMAH. A controlled oxygen content is provided in the treatment solution or in an environment in the process chamber to achieve a target etch selectivity of the silicon, or a target etch uniformity across the layer, feature or structure of silicon, or both by the treatment solution.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: April 9, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Wallace P. Printz, Shuhei Takahashi, Naoyuki Okamura, Masami Yamashita, Derek W. Bassett, Antonio Luis Pacheco Rotondaro
  • Patent number: 10236261
    Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Yi-Feng Chang, Lung-Yuan Wang
  • Patent number: 10236266
    Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 19, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou, Katsumi Takano, Mitsuru Hiroshima
  • Patent number: 10224478
    Abstract: A one-dimensional magnetic field sensor comprises a support, a single elongated magnetic field concentrator or two magnetic field concentrators, which are separated by a first gap, and at least one magnetic sensor element. The magnetic field concentrator, or both thereof, consists of at least two parts which are separated from each other by second gaps. A two-dimensional magnetic field sensor comprises a support, a single magnetic field concentrator which consists of at least three parts which are separated from each other by gaps, and at least two magnetic sensor elements.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 5, 2019
    Assignee: Interglass Technology AG
    Inventor: Robert Racz
  • Patent number: 10170312
    Abstract: Present disclosure provides a method for manufacturing a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer, including providing the semiconductor wafer with a first dopant concentration of a dopant having a first conductivity type, forming a polysilicon layer over the front surface, removing the polysilicon layer from the front surface, and depositing the epitaxial layer at the front surface with a second dopant concentration of the dopant having the first conductivity type under a predetermined temperature. A transition width of the dopant having the first conductivity type across the semiconductor wafer and the epitaxial layer is controlled by the predetermined temperature to be at least about 0.75 micrometer. A semiconductor device and a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer are also disclosed.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Pu-Fang Chen, Wei-Zhe Chang, Shi-Jieh Lin, Victor Y. Lu