Abstract: A method of forming an array substrate, the array substrate and a display device are provided. The method of forming the array substrate includes: in a case that a display unit is formed on one of two opposite surfaces of a base substrate and a driving circuit is formed on the other of the two opposite surfaces of the base substrate, performing a roughening treatment on edge regions of the two opposite surfaces of the base substrate and a side surface of the base substrate connecting the edge regions of the two opposite surfaces, to form a roughened region; and forming, at the roughened region, a metal wiring connecting a signal input terminal of the display unit and a signal output terminal of the driving circuit.

Abstract: A display device includes a driving gate electrode, a scan line separate from the driving gate electrode, a data line, a driving voltage line, and a semiconductor area including a first channel region overlapping the driving gate electrode and a shielding area overlapping the first data line. The display device also has a control line which includes a main line portion and a detour portion. The main line portion and the detour portion extend in different directions, and the semiconductor area includes a second channel region overlapping the first portion of the detour portion.

Abstract: A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.

Abstract: Embodiments of the present application provide a semiconductor structure and a manufacturing method therefor. A buffer layer is disposed on a substrate layer, and the buffer layer includes a first buffer layer and a second buffer layer. By doping a transition metal in the first buffer layer, a deep level trap may be formed to capture background electrons, and diffusion of free electrons toward the substrate may also be avoided. By decreasing a doping concentration of the transition metal in the second buffer layer, a tailing effect is avoided and current collapse is prevented. By doping periodically the impurity in the buffer layer, the impurity may be as an acceptor impurity to compensate the background electrons, and then a concentration of the background electrons is reduced. By using the periodic doping method, dislocations, caused by doping, in the buffer layer may be effectively reduced.

Abstract: The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a display area and a non-display area, and the non-display area has GOA regions. The display panel further includes a first substrate, an array substrate, and an anti-deformation layer. In the present disclosure, the anti-deformation layer is disposed on a lower surface of the first substrate at a position corresponding to the GOA regions. Metal material of the GOA regions is same as metal material of the anti-deformation layer, so that metal expansion coefficient of upper and lower surfaces of the first substrate are same, thereby effectively preventing warpage of the first substrate and the array substrate.

Abstract: Various forms of MgxGe1-xO2-x are disclosed, where the MgxGe1-xO2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of MgxGe1-xO2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of MgxGe1-xO2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

Abstract: Leadframes for semiconductor devices are manufactured by providing a laminar substrate of laser direct structuring material, the laminar substrate comprising first and second opposed surfaces, applying laser beam processing to the substrate to provide a first pattern of electrically-conductive formations at the first surface, a second pattern of electrically-conductive formations at the second surface and electrically-conductive vias through the substrate between the first surface and the second surface. Electrically-conductive material is formed, for instance via electrolytic or electroless growth of electrically-conductive material such a copper onto the first and second pattern of electrically-conductive formations as well as onto the electrically-conductive vias provided by applying laser beam processing to the substrate.

Abstract: The application discloses an array substrate, a manufacturing method of the array substrate and a display panel. It includes a thin film transistor, and the thin film transistor includes a substrate, a Metal 1, an insulating layer, a semiconductor layer, a barrier layer, a Metal 2, a first passivation layer and a pixel electrode; the Metal 2 includes a source electrode and a drain electrode. A connecting groove is arranged on the barrier layer corresponding to the position of the source electrode and the drain electrode, one end of the connecting groove is connected to the source electrode and the semiconductor layer, and the other end is connected to the drain electrode and the semiconductor layer.

Abstract: An array substrate and a display screen, where the array substrate includes a display area and a wiring area located on one side of the display area, the wiring area includes an upper wiring layer and a lower wiring layer laminated with the upper wiring layer, the upper wiring layer and the lower wiring layer are separated by an insulating layer group, the insulating layer group includes an insulating sub-layer and an insulating organic compensator formed on the insulating sub-layer, the insulating organic compensator is configured to compensate for at least part of a recess on an upper surface of the insulating sub-layer.

Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

Abstract: Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.

Abstract: A semiconductor device includes a stacked structure including insulating layers and conductive layers alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure passing through the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure and each including a first surface and a second surface, wherein the first surface faces each of the insulating layers and is flat and the second surface faces the channel structure and includes a curved surface, and a memory layer interposed between the stacked structure and the channel structure and filling a space between the insulating patterns, wherein a sidewall of each of the conductive layers is located on an extending line of a sidewall of the hard mask pattern and the insulating patterns protrude farther towards the channel structure than the sidewall of the hard mask pattern.

Abstract: A piezoelectric substrate manufacturing device that includes first and electrodes that face each other with a piezoelectric substrate interposed therebetween; a cover that surrounds the second electrode such that the leading end of the second electrode is exposed; a supply unit that supplies a processing gas to an internal space of the cover; a processing unit that performs surface processing on the piezoelectric substrate by applying a voltage between the first and second electrodes causing the processing gas to change into plasma; a detector that is provided outside the cover with its relative position fixed with respect to the second electrode; a measurement unit that measures the thickness of the piezoelectric substrate using the detector; a driving unit that changes the relative positions of the first and second electrodes; and a control unit that controls the supply unit, the processing unit, the measurement unit, and the driving unit.

Abstract: An electronic package is provided and has a packaging substrate including a ground pad and a power pad. The power pad surrounds at least three directions of the ground pad so as to increase the footprint of the power pad on the packaging substrate, thereby avoiding cracking of an electronic element disposed on the packaging substrate and effectively reducing the voltage drop.

Abstract: A metal wiring film, a method for fabricating the same, and a thin film transistor. The metal wiring film includes: a first film layer formed by a nickel-copper alloy, a mass percentage of nickel in the nickel-copper alloy ranges from 30% to 70%; a second film layer disposed above the first film layer, a material forming the second film layer is an aluminum-neodymium alloy, and the mass percentage of neodymium in the aluminum-neodymium alloy ranges from 1% to 5%; a third film layer disposed above the second film layer, a material forming the third film layer is the same as the material forming the first film layer.

Abstract: A TFT substrate includes a transmission and/or reception region including a plurality of antenna unit regions, and a non-transmission and/or reception region other than the transmission and/or reception region. The TFT substrate includes a dielectric substrate, and the plurality of antenna unit regions, a plurality of gate bus lines, and a plurality of source bus lines supported on the dielectric substrate. Each of the antenna unit regions includes a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate further includes a first conductive layer including one of a gate electrode or a source electrode of the TFT, a first insulating layer on the first conductive layer, and a plurality of terminal sections provided in the non-transmission and/or reception region.

Abstract: Methods and apparatus for forming a thin film transistor (TFT) having a metal oxide layer. The method may include forming an amorphous metal oxide layer and treating the metal oxide layer with a silicon containing gas or plasma including Si4+ ions. The silicon treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.

Abstract: A semiconductor device is provided with circuit patterns and dummy patterns. The circuit patterns facilitate circuit operations and the dummy patterns do not facilitate circuit operations. The dummy patterns are formed as patterns at which crystal defects are more likely to be caused by stress than the circuit patterns.

Abstract: Disclosed are a thin film transistor (TFT) including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving, a gate driver including the TFT, and a display device including the gate driver. The TFT includes first oxide semiconductor layer consisting of indium-gallium-zinc-tin oxide (IGZTO) and a second oxide semiconductor layer including indium-gallium-zinc oxide (IGZO). A content ratio (Ga/In) of gallium (Ga) to indium (In) of the second oxide semiconductor layer is higher than a content (Ga/In) of Ga to In of the first oxide semiconductor layer, and a content ratio (Zn/In) of zinc (Zn) to In of the second oxide semiconductor layer is higher than a content (Zn/In) of Zn to In of the first oxide semiconductor layer.