Abstract: 3D integrated circuit (3DIC) device architecture is disclosed for monolithically heterogeneous integration of III-V devices over Si-CMOS devices with high-quality (HQ) integrated passives devices (IPD) or re-distributed layers (RDL). In addition, a thermal spreader may be added over the upper III-V tier to enhance device power performance (e.g., PAE for PA) and device reliability (e.g., with a reduced Tj/junction temperature).

Abstract: An array substrate includes a substrate, a packaging layer, and at least one sensor. The packaging layer is over the substrate. Each sensor includes a sensing thin-film transistor and a sensing unit, electrically coupled with each other. The sensing thin-film transistor is between the package layer and the substrate, and the sensing unit is over a side of the package layer away from the substrate. The array substrate can also include a plurality of display thin-film transistors. The sensing thin-film transistor in each sensor can be at substantially same film layers, or of a same structure and a same type, as each display thin-film transistor.

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

Abstract: A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes a first electrode having a first groove group, a second groove group and a non-hollow portion; the first groove group includes a plurality of hollow first grooves arranged successively, each first groove includes a first end and a second end arranged along an extending direction thereof; the second groove group includes a plurality of hollow second grooves arranged successively, each second groove includes a third end and a fourth end arranged along an extending direction thereof, and a third end is on a side of the fourth end adjacent to the first groove group; and the third end of at least one second groove is staggered with respect to the second end of the first groove adjacent to the third end.

Abstract: The disclosed technology generally relates to a memory selector and to a memory device including the memory selector, and more particularly to the memory selector and the memory device implemented in a crossbar memory architecture. In one aspect, a memory selector for a crossbar memory architecture comprises a metal bottom electrode, a metal top electrode and an intermediate layer stack between and in contact with the metal top and bottom electrodes. A bottom Schottky barrier having a bottom Schottky barrier height (?B) is formed at the interface between the metal bottom electrode and the intermediate layer stack. A top Schottky barrier having a top Schottky barrier height (?T) is formed at the interface between the metal top electrode and the intermediate layer stack. The disclosed technology further relates to a random access memory (RAM) and a memory cell including the memory selector.

Abstract: Through selective incorporation of high carrier mobility graphene monolayers into low cost, NIR-sensitive SiGe detector layer structures, a device combining beneficial features from both technologies can be achieved. The SiGe in such hybrid SiGe/graphene detector devices serves as the NIR absorbing layer, or as the quantum dot material in certain device iterations. The bandgap of this SiGe layer where absorption of photons and photogeneration of carriers mainly takes place may be tuned by varying the concentrations of Ge in the SixGe1-x material. This bandgap and the thickness of this layer largely impact the degree and spectral characteristics of absorption properties, and thus the quantum efficiency or responsivity of the device. The main function and utility of the graphene monolayers, which are nearly transparent to incident light, is to facilitate the extraction and transport of electron and hole carriers from the SiGe absorbing layer through the device.

Abstract: An electrostatic protection circuit and a manufacturing method thereof, an array substrate and a display apparatus in the field of display technology are provided. This electrostatic protection circuit includes: a discharge sub-circuit, a buffer sub-circuit and an electrostatic protection line, wherein the electrostatic protection line is a common electrode line; the buffer sub-circuit includes a third transistor and a fourth transistor; a gate and a second electrode of the third transistor are both connected to a first electrode of the fourth transistor, and the first electrode of the third transistor is connected to a signal line; a gate and a second electrode of the fourth transistor are both connected to the signal line.

Abstract: The present application provides a method of manufacturing an array substrate, the array substrate, and a display device. In the method, a photoresist layer is removed by a plasma cleaning technique after performing etching to prevent a gate electrode of the array substrate from contacting a stripping solution, thereby preventing a metal layer of the gate electrode from being corroded by the stripping solution.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a second electrode layer formed over the first electrode layer, and a second spacer formed on a sidewall of the second electrode layer. The second spacer is in direct contact with an interface between the second electrode layer and a first dielectric layer.

Abstract: A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode.

Abstract: A composite thin film includes N thin film layers stacked one over another in sequence from a first thin film layer to an N-th thin film layer. N is an integer satisfying 3?N?9. The N thin film layers are nano-ZnO thin films. A nano-ZnO particle size of the nano-ZnO thin films gradually increases or decreases from the first thin film layer to the N-th thin film layer.

Abstract: An optical device includes a first conductive layer, a first junction layer, a light absorption layer, a second junction layer, and a second conductive layer. The first junction layer is disposed on the first conductive layer. The light absorption layer is disposed on the first junction layer, wherein the light absorption layer includes a plurality of unit cells, each of the unit cells includes a plurality of pillar structures, and the pillar structures of each of the unit cells are different sizes. The second junction layer is disposed on the light absorption layer. The second conductive layer is disposed on the second junction layer.

Abstract: A semiconductor device having a back-side field plate includes a buffer layer that includes a first compound semiconductor material, where the buffer layer is epitaxial to a crystalline substrate. The semiconductor device also includes field plate layer that is disposed on a surface of the buffer layer. The semiconductor device further includes a first channel layer disposed over the field plate layer, where the first channel layer includes the first compound semiconductor material. The semiconductor device further includes a region comprising a two-dimensional electron gas, where the two-dimensional electron gas is formed at an interface between the first channel layer and a second channel layer. The semiconductor device additionally includes a back-side field plate that is formed by a region of the field plate layer and is electrically isolated from other regions of the field plate layer.

Abstract: The superior electronic and mechanical properties of 2D-layered transition metal dichalcogenides and other 2D layered materials could be exploited to make a broad range of devices with attractive functionalities. However, the nanofabrication of such layered-material-based devices still needs resist-based lithography and plasma etching processes for patterning layered materials into functional device features. Such patterning processes lead to unavoidable contaminations, to which the transport characteristics of atomically-thin layered materials are very sensitive. More seriously, such lithography-introduced contaminants cannot be safely eliminated by conventional material wafer cleaning approaches. This disclosure introduces a rubbing-induced site-selective growth method capable of directly generating few-layer molybdenum disulfide device patterns without the need of any additional patterning processes.

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

Abstract: The present invention provides a display panel and a display module. The display panel comprises at least two pixel units. Each pixel units comprises a substrate, a thin film transistor (TFT) disposed on the substrate, and a pixel electrode disposed on the thin film transistor. The thin film transistor and the pixel electrode disposed in the same pixel unit are insulated from each other. The thin film transistor disposed in the pixel unit is electrically connected to a pixel electrode disposed in another pixel unit, which is disposed parallel to the pixel unit.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.

Abstract: An embodiment of the present application provides a preparation method of a mask assembly, including: fixing, after stretching and aligning a blocking, the blocking on a side of a frame; opening at least one stretching align hole and at least one evaporation align mark in the fixed blocking and frame; fixing, after stretching and aligning a mask sheet, the mask sheet on a side of the blocking away from the frame according to the stretching align hole; and opening at least one evaporation align mark in the fixed mask sheet to obtain the mask assembly.

Abstract: A porous region structure and a method of fabrication thereof are disclosed. The porous region structure is characterized by having a hard mask interface region with non-uniform pores sealed and thereby excluded functionally from the structure. The sealing of the hard mask interface region is done using a hard mask deposited on top of an anodization hard mask used to define the porous region of the structure. By excluding the hard mask interface region, the porosity ratio and the equivalent specific surface of the porous region structure can be controlled or quantified with higher accuracy. Corrosion due to exposure of an underlying metal layer of the structure is also significantly reduced by sealing the hard mask interface region.

Abstract: Provided is an opto-electronic device having low dark noise and a high signal-to-noise ratio. The opto-electronic device may include: a first semiconductor layer doped to have a first conductivity type; a second semiconductor layer disposed on an upper surface of the first semiconductor layer and doped to have a second conductivity type electrically opposite to the first conductivity type; a transparent matrix layer disposed on an upper surface of the second semiconductor layer; a plurality of quantum dots arranged to be in contact with the transparent matrix layer; and a first electrode provided on a first side of the transparent matrix layer and a second electrode provided on a second side of the transparent matrix layer opposite to the first side, wherein the first electrode and the second electrode are electrically connected to the second semiconductor layer.