Abstract: A semiconductor apparatus and a method of fabricating the same are provided. The method includes sequentially depositing a gate electrode material and a sacrificial insulating layer on a semiconductor substrate, patterning the gate electrode material and the sacrificial insulating layer to form one or more holes exposing a surface of the semiconductor substrate, forming a gate insulating layer on an inner sidewall of the hole, forming one or more pillar patterns each filled in the hole and recessed on a top thereof, forming a contact unit and an electrode unit on the pillar pattern, removing a patterned sacrificial insulating layer and forming a spacer nitride material on the semiconductor substrate from which the patterned sacrificial insulating layer is removed, and removing portions of the spacer nitride material and a patterned gate electrode material between the pillar patterns.

Abstract: Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate Source and body regions are formed by implanting dopants onto the filled trenches. This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

Abstract: The present invention provides a pattern substrate structure for light emitting angle convergence and a light emitting diode device using the same. The pattern substrate structure has a plurality of enclosed geometric regions defined by at least three stripe-shaped parts on a substrate to provide the light reflection effect through the uneven surface of the substrate and thereby converge the light emitting angle of the light emitting diode element into 100˜110 degrees. Therefore, the illuminant efficiency of the light emitting diode device using the pattern substrate structure is substantially raised because of the improved directivity.

Abstract: Exemplary embodiments of the present invention relate to light emitting devices including strontium oxyorthosilicate-type phosphors. The light emitting device includes a light emitting diode, which emits light in the UV or visible range, and phosphors disposed around the light emitting diode to absorb light emitted from the light emitting diode and emit light having a different wavelength from the absorbed light. The phosphors include an oxyorthosilicate phosphor having a general formula of Sr3-x-y-zCaxMIIySiO5: Euz with a calcium molar fraction in the range of 0<x?0.05.

Abstract: A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region.

Abstract: An organic electroluminescent display includes a first substrate, a pixel, a gate line, a data line, a switching transistor, a power signal line, a driving transistor, and a storage capacitor. The storage capacitor includes first, second, and third electrodes. The first electrode is on the first substrate, and the second electrode includes the same material as the gate line. The second electrode is on the first electrode and insulated from the first electrode. The third electrode is insulated from and on the second electrode, and the third electrode is insulated from the first electrode.

Abstract: MEMS devices, packaged MEMS devices, and methods of manufacture thereof are disclosed. In one embodiment, a microelectromechanical system (MEMS) device includes a first MEMS functional structure and a second MEMS functional structure. An interior region of the second MEMS functional structure has a pressure that is different than a pressure of an interior region of the first MEMS functional structure.

Abstract: A material is manufactured from a single piece of semiconductor material. The semiconductor material can be an n-type semiconductor. Such a manufactured material may have a top layer with a crystalline structure, transitioning into a transition layer, further transitioning into an intermediate layer, and further transitioning to the bulk substrate layer. The orientation of the crystalline pores of the crystalline structure align in layers of the material. The transition layer or intermediate layer includes a material that is substantially equivalent to intrinsic semiconductor. Also described is a method for manufacturing a material from a single piece of semiconductor material by exposing a top surface to an energy source until the transformation of the top surface occurs, while the bulk of the material remains unaltered. The material may exhibit photovoltaic properties.

Abstract: Provided are methods of surface treatment of nanocrystal quantum dots after film deposition so as to exchange the native ligands of the quantum dots for exchange ligands that result in improvement in charge extraction from the nanocrystals.

Abstract: Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.

Abstract: A semiconductor device may include a first transistor, a second transistor connected in series to the first transistor through a first junction, and a third transistor connected in series to the second transistor through a second junction. Here, a high voltage is supplied to one of the first and second junctions, and a turn-off voltage is supplied to a gate of the second transistor.

Abstract: Disclosed is an organic light emitting display device improving light efficiency by forming a metal layer having a nanometer thickness on a protective layer formed in order to protect the organic light emitting diode.

Abstract: Disclosed herein are a printed circuit board, including an insulating layer; a circuit wiring formed on one surface or both surfaces of the insulating layer and made of a single metal layer; a via formed in the insulating layer for interconnecting the circuit wirings through the insulating layer; and a pad layer formed on one surface or both surfaces of the insulating layer and adhered to an end portion of the via, the pad layer being formed of a central portion extended from the via and an outside portion made of the same single metal layer as the circuit wiring, and a method for manufacturing the same.

Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

Abstract: A substrate including a body comprising a Group III-V material and having an upper surface, the body comprising an offcut angle defined between the upper surface and a crystallographic reference plane, and the body further having an offcut angle variation of not greater than about 0.6 degrees.

Abstract: A device and a method of forming the same are disclosed. The device comprises a substrate and a thin film. The substrate is characterized by a first coefficient of thermal expansion. The thin film is attached to a surface of the substrate, and is characterized by a second coefficient of thermal expansion. The thin film includes first and second layers in states of compression, and a third layer in a state of tension, the third layer being positioned between the first and second layers. The thin film is in a net state of tension within a temperature range.

Abstract: A silicon structure is fabricated determining a pattern for wire trenches and air gaps. The wire trenches are created, and certain trenches are used as air gaps. The remaining wire trenches are used for metallization of inter connecting wires.

Abstract: In one embodiment, a semiconductor device includes a multi-portion shield electrode structure formed in a drift region. The shield electrode includes a wide portion formed in proximity to a channel side of the drift region, and a narrow portion formed deeper in the drift region. The narrow portion is separated from the drift region by a thicker dielectric region, and the wide portion is separated from the drift region by a thinner dielectric region. That portion of the drift region in proximity to the wide portion can have a higher dopant concentration than other portions of the drift region.

Abstract: A semiconductor device comprises: a semiconductor structure formed with openings for exposing pads on an one surface thereof, a first conductive layer formed in the openings to make the one surface of the semiconductor structure more uniform, and conductive patterns formed on portions of the one surface of the semiconductor structure including the first conductive layers.

Abstract: A MOS RF surveillance and/or identification tag, and methods for its manufacture and use. The tag includes an interposer, an antenna/inductor, and integrated circuitry on the interposer. The integrated circuitry has a lowest layer in physical contact with the interposer. The method of manufacture includes forming a lowest layer of integrated circuitry on an interposer, forming successive layers of the integrated circuitry on the lowest layer of integrated circuitry, and attaching an electrically conductive functional layer to the interposer. Alternatively, an electrically conductive structure may be formed from a functional layer attached to the interposer. The method of use includes causing/inducing a current in the present tag sufficient for it to generate, reflect or modulate a detectable electromagnetic signal, detecting the signal, and optionally, processing information conveyed by the detectable electromagnetic signal.