Abstract: Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer.

Abstract: A semiconductor device has a semiconductor body including opposing bottom and top sides, a surface surrounding the semiconductor body, an active semiconductor region formed in the semiconductor body, an edge region surrounding the active semiconductor region, a first semiconductor zone of a first conduction type formed in the edge region, an edge termination structure formed in the edge region at the top side, and a shielding structure arranged on that side of the edge termination structure facing away from the bottom side. The shielding structure has a number of N1?2 first segments and a number of N2?1 second segments. Each of the first segments is electrically connected to each of the other first segments and to each of the second segments, and each of the second segments has an electric resistivity higher than an electric resistivity of each of the first segments.

Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.

Abstract: The disclosure provides a pixel structure, a manufacturing method of a pixel structure, an array substrate, a display panel, and a display device. The pixel structure includes a plurality of data lines and a plurality of scan lines, and a plurality of pixel units formed by intersecting the plurality of data lines with the plurality of scan lines. A pixel unit corresponds to one of the plurality of data lines and one of the plurality of scan lines. The pixel unit includes a pixel electrode and a TFT. The pixel electrode includes a plurality of slits having corners. The pixel electrode of the pixel unit in a row is electrically connected to a TFT of a pixel unit in a preceding adjacent row of the pixel electrode of the pixel unit, and the corner of the pixel electrode close to the TFT extends toward the thin film transistor.

Abstract: A thin film transistor (TFT) array panel and a manufacturing method thereof are disclosed. A contact hole may be formed to expose a pad disposed on a substrate of the TFT array panel. A first layer of a connecting member is formed with the same layer as a first field generating electrode and is disposed in the contact hole. A second passivation layer is disposed in the TFT array panel, but is removed at a region where the contact hole is formed and portions of the second passivation layer that cover the first layer of the connecting member. A second layer of the connecting member is formed on the first layer of the connecting member.

Abstract: Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. Some embodiments include a memory unit which includes a memory cell and a select device electrically coupled to the memory cell. The select device has a selector region between a pair of electrodes. The selector region contains semiconductor doped with one or more of nitrogen, oxygen, germanium and carbon. The select device has current versus voltage characteristics which include snap-back voltage behavior.

Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.

Abstract: Some embodiments include a construction having oxygen-sensitive structures directly over spaced-apart nodes. Each oxygen-sensitive structure includes an angled plate having a horizontal portion along a top surface of a node and a non-horizontal portion extending upwardly from the horizontal portion. Each angled plate has an interior sidewall where an inside corner is formed between the non-horizontal portion and the horizontal portion, an exterior sidewall in opposing relation to the interior sidewall, and lateral edges. Bitlines are over the oxygen-sensitive structures, and have sidewalls extending upwardly from the lateral edges of the oxygen-sensitive structures. A non-oxygen-containing structure is along the interior sidewalls, along the exterior sidewalls, along the lateral edges, over the bitlines, and along the sidewalls of the bitlines. Some embodiments include memory arrays, and methods of forming memory cells.

Abstract: After forming a plurality of gate structures over a substrate having a plurality of active regions separated from each other by at least one shallow trench isolation (STI) regions, inter-gate dielectric contact structures extending through an interlevel dielectric (ILD) layer that surrounds the gate structures are formed. Each inter-gate dielectric contact structure encloses a corresponding gate structure and is in contact with a dielectric gate cap and a dielectric gate spacer of the corresponding gate structure and a portion of the at least one STI region abutting the dielectric gate spacer of the corresponding gate structure. The inter-gate dielectric contact structure is electrically insulated from a gate conductor in the corresponding gate structure by the dielectric gate cap and the dielectric gate spacer and serves as a control gate in a memory cell of a flash memory array.

Abstract: Embodiments of the invention relate to a process for fabricating a silicon-on-insulator structure comprising the following steps: providing a donor substrate and a support substrate, only one of the substrates being covered with an oxide layer; forming, in the donor substrate, a weak zone; plasma activating the oxide layer; bonding the donor substrate to the support substrate in a partial vacuum; implementing a bond-strengthening anneal at a temperature of 350° C. or less causing the donor substrate to cleave along the weak zone; and carrying out a heat treatment at a temperature above 900° C. A transition from the temperature of the bond-strengthening anneal to the temperature of the heat treatment may be achieved at a ramp rate above 10° C./s.

Abstract: A semiconductor device includes a circuit substrate which is configured with an insulative substrate formed of a ceramic material and provided on its one surface with an electrode formed of a copper material, and a power semiconductor element bonded with the electrode using a sinterable silver-particle bonding material, wherein the electrode has a Vickers hardness of 70 HV or more in its portion from the bonding face with the power semiconductor element toward the insulative substrate to a depth of 50 ?m, and has a Vickers hardness of 50 HV or less in its portion at the side toward the insulative substrate.

Abstract: A method includes forming a first metal liner conformally along a sidewall and a bottom of a contact opening. A second metal liner is formed above and in direct contact with the first metal liner, a grain size of the first metal liner is larger than a grain size of the second metal liner. A barrier layer is formed above and in direct contact with the second metal liner and the contact opening is filled with a conductive material to form a middle-of-the-line contact.

Abstract: The present disclosure relates to an organic image sensor and an associated method. By inserting an inorganic protective layer between an electrode and an organic photo active region of the image sensor, the organic photo active region is protected from moisture, oxygen or following process damage. The inorganic protective layers also help to suppress the leakage in the dark. In some embodiments, the organic image sensor comprises a first electrode, an organic photoelectrical conversion structure disposed over the first electrode and a second electrode disposed over the organic photoelectrical conversion structure. The organic image sensor further comprises a first protective structure covering a top surface and a sidewall of the organic photoelectrical conversion structure.

Abstract: This invention describes a hermetically sealed package which can be implanted in the body. The package comprise of stacked substrates where surface of one substrate hosts biosensors which are exposed to body fluids to monitor concentrations of substances selected from analytes, metabolites, and proteins, and body physiological parameters. The structure protects from body fluids devices that interface with the biosensor electrodes for electronic data processing, powering, and wireless communication. Biosensor electrodes are electrically connected to various electronic, optoelectronic, MEM devices using novel partial silicon vias (PSVs) that prevents leakage of body fluids. Various devices are located on different substrates which are stacked to save surface area. One of the substrate forms the cover plate which permits light for powering as well as sending receiving coded data including the analyte levels.

Abstract: A nitride semiconductor light emitting device includes a first coat film of aluminum nitride or aluminum oxynitride formed at a light emitting portion and a second coat film of aluminum oxide formed on the first coat film. The thickness of the second coat film is at least 80 nm and at most 1000 nm. Here, the thickness of the first coat film is preferably at least 6 nm and at most 200 nm.

Abstract: A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

Abstract: An electroluminescent device, comprising: a substrate; a first electrode and a second electrode disposed on the substrate; and an electroluminescent layer sandwiched between the first electrode and the second electrode, wherein at least one of the first and second electrodes is configured to have a grating structure; and wherein the grating structure has a grating period within a range of 0.9˜1.1 times of a wavelength of a light wave generated in the electroluminescent layer.

Abstract: This disclosure relates generally to package substrates with multiple embedded dice wherein each of the embedded dice can be connected directly to a bus of the package substrate without being routed through another die. The package substrate may be configured as a bumpless build up layer (BBUL) substrate.

Abstract: A semiconductor light emitting device includes a light-transmissive substrate, a light-transmissive buffer layer disposed on the light-transmissive substrate, and a light emitting structure. The light-transmissive buffer layer includes a first layer and a second layer having different refractive indices and disposed alternately at least once. The light emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially disposed on the buffer layer.

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.