Abstract: An electrical circuit having a spatially-efficient MEMS architecture, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

Abstract: This invention provides a method for chip scale package and a chip scale package structure. The chip scale package structure includes: a semiconductor substrate, on which sets a plurality of contact bonding pads being connected with semiconductor devices; and a plurality of bumps respectively attached to all of the contact bonding pads. The semiconductor substrate is divided into several regions according to different distances from a central point. The contact bonding pads and the bumps in the region which is closest to the central point are the smallest, while the contact bonding pads and the bumps in the region which is farthest to the central point are the largest. The invention effectively improves the situation that the bumps at the edge tend to flake off easily; in addition, it avoids short-circuit caused by bridging between the bumps.

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract: The present application relates to a light-emitting device and method of manufacturing the same. The device includes a lower portion, and vertical light-emitting structures disposed on the lower portion. A conductive member partially surrounds the vertical light-emitting structures, and reflective members are disposed between the vertical light-emitting structures. The reflective members reflect light that is emitted in a lateral direction from the vertical light-emitting structures to minimize the number of times that light emitted in a lateral direction from the vertical light-emitting structure is transmitted through the light-absorbing member, thereby increasing a luminous efficiency.

Abstract: A method of manufacturing a semiconductor element includes forming a first bonding layer containing a metal, which forms a eutectic crystal with Au, on a first substrate to provide a first laminated body. The method also includes forming an element structure layer having a semiconductor layer on a second substrate. The method also includes forming a second bonding layer on the element structure layer to provide a second laminated body. The second bonding layer has a metal underlayer containing a metal, which forms a eutectic crystal with Au. The second bonding layer also has a surface layer that contains Au. The method also includes performing heating pressure-bonding on the first and second laminated bodies with the first and second bonding layers facing each other. The heating temperature of the second substrate in the heating pressure-bonding is higher than the heating temperature of the first substrate.

Abstract: An organic EL display panel has a transistor array substrate, an inter-layer insulation film, pixel electrodes, an organic EL layer, and a common electrode. The transistor array substrate has drive units, including TFT elements. The inter-layer insulation film covers the transistor array substrate, and has contact holes corresponding to the drive units. The pixel electrodes on the inter-layer insulation film correspond to the drive units, and are electrically connected thereto via the contact holes. The organic EL layer covers regions where the pixel electrodes are and are not disposed. The common electrode covers the entire organic EL layer. Organic EL layer regions corresponding to the contact holes of the inter-layer insulation film and between neighboring pixel electrodes have greater electrical resistance than other regions.

Abstract: A semiconductor device including a chip stack structure having a plurality of semiconductor chips, the semiconductor chips being stacked such that they are electrically connected using through-electrodes, and a support frame attached to a side surface of the chip stack structure.

Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.

Abstract: A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.

Abstract: A transistor may include a channel layer formed of an oxide semiconductor. The oxide semiconductor may include GaZnON, and a proportion of Ga content to a total content of Ga and Zn of the channel layer is about 0.5 to about 4.5 at %.

Abstract: A variable resistance memory device includes a plurality of cell blocks each of which includes a plurality of first lines extending in parallel to each other along a first direction, a plurality of second lines extending in parallel to each other along a second direction crossing the first direction, and a plurality of memory cells including variable resistance layers arranged at intersections of the plurality of first lines and the plurality of second lines and a plurality of selection units coupled to the plurality of first lines and coupling two neighboring cell blocks.

Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.

Abstract: A semiconductor light emitting element has a cross-sectional structure comprising a support substrate, a semiconductor lamination located over the support substrate, and a joint layer located between the semiconductor lamination and the support substrate, containing a first jointing layer located on the semiconductor lamination side and a second jointing layer located on the support substrate side. In the plan view, the semiconductor lamination has corner portions and side portions along the periphery, the first jointing layer is encompassed by the second jointing layer, the second jointing layer is encompassed by the semiconductor lamination, and an annular region defined between outlines of the semiconductor lamination and of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths of the first portions being narrower than widths of the second portions.

Abstract: Disclosed is a substrate for a flexible device which, when a TFT is produced on a flexible substrate in which a metal layer and a polyimide layer are laminated, can suppress deterioration of the electrical performance of the TFT due to the surface irregularities of the metal foil surface and can suppress detachment or cracks of the TFT. Also disclosed is a substrate for a thin film element which has excellent surface smoothness and is capable of suppressing deterioration of the characteristics of thin film elements. Also disclosed are methods for manufacturing substrates for thin film elements.

Abstract: A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer. In this manner, the via hole may be coated with a conductive element that may serve as a conductive path between a common electrode and the drain of the transistor.

Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.

Abstract: An OLED display includes an organic layer formed using a printing method. A method for manufacturing the OLED display includes: forming a pixel circuit on a substrate; forming a planarization layer on the substrate to cover the pixel circuit, where the planarization layer includes heat generation particles; forming a pixel electrode and a pixel defining layer on the planarization layer; forming an organic layer by discharging ink on the pixel electrode and drying the ink by generating heat from the heat generation particles through microwave irradiation; and forming a common electrode on the organic layer.

Abstract: The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.

Abstract: A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.

Abstract: According to one embodiment, a semiconductor device includes an insulating film, a catalytic layer and a wiring layer. The insulating film has a hole. The catalytic layer is formed at the bottom of the hole, at the peripheral wall of the hole, and on the upper surface of the insulating film outside the hole. A contact is formed of a carbon nanotube provided on the portion of the catalytic layer at the bottom of the hole. The wiring layer is formed of graphene and provided on the catalytic layer outside the hole in contact with the carbon nanotube. The catalytic layer at the bottom of the hole is a perforated film, and the catalytic layer outside the hole is a continuous film.