Abstract: A magneto-electronic device includes a first electrode, a second electrode spaced apart from the first electrode, and an electric-field-controllable magnetic tunnel junction arranged between the first electrode and the second electrode. The electric-field-controllable magnetic tunnel junction includes a first ferromagnetic layer, an insulating layer formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the insulating layer. The first and second ferromagnetic layers have respective first and second magnetic anisotropies that are alignable substantially parallel to each other in a first state and substantially antiparallel in a second state of the electric-field-controllable magnetic tunnel junction.

Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.

Abstract: An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device comprises a N+ well, a P doping region, a first N doping region, a plurality of N sub-doping regions, a first N+ doping region, a first P+ doping region, a second N+ doping region, and a second doping region. The P doping region is disposed in the N+ well. The first N doping region is disposed in the P doping region. The plurality of N sub-doping regions is disposed in parallel in the P doping region. The first N+ doping region is disposed in the first N doping region. The first P+ doping region is disposed in the first N doping region. The second N+ doping region is disposed in the P doping region.

Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

Abstract: A high temperature micro-glassblowing process and a novel inverted-wineglass architecture that provides self-aligned stem structures. The fabrication process involves the etching of a fused quartz substrate wafer. A TSG or fused quartz device layer is then bonded onto the fused quartz substrate, creating a trapped air pocket or cavity between the substrate and the TSG device layer. The substrate and TSG device layer 14 are then heated at an extremely high temperature of approximately 1700° C., forming an inverted wineglass structure. Finally, the glassblown structure is cut or etched from the substrate to create a three dimensional wineglass resonator micro-device. The inverted wineglass structure may be used as a high performance resonator for use as a key element in precision clock resonators, dynamic MEMS sensors, and MEMS inertial sensors.

Abstract: An apparatus is provided for modulating the photon output of a plurality of free standing quantum dots. The apparatus comprises a first electron injection layer (210, 310, 410) disposed between a first electrode (212, 312, 412) and a layer (208, 308, 408) of the plurality of free standing quantum dots. A hole transport layer (206, 306, 406) is disposed between the layer (208, 308, 408) of the plurality of quantum dots and a second electrode (204, 304, 404). A light source (224, 324, 424) is disposed so as to apply light to the layer (208, 308, 408) of the plurality of free standing quantum dots. The photon output of the layer (208, 308, 408) of the plurality of free standing quantum dots is modulated by applying a voltage to the first and second electrodes (212, 312, 412, 204, 304, 404).

Abstract: A method for fabricating a non-volatile memory semiconductor device is disclosed. The method includes the steps of providing a substrate; forming a gate pattern on the substrate, wherein the gate pattern comprises a first polysilicon layer on the substrate, an oxide-nitride-oxide (ONO) stack on the first polysilicon layer, and a second polysilicon layer on the ONO stack; forming an oxide layer on the top surface and sidewall of the gate pattern; performing a first etching process to remove part of the oxide layer; and performing a second etching process to completely remove the remaining oxide layer.

Abstract: Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polyimide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Abstract: A light emitting diode (LED) assembly may include an LED semiconductor attached to a first surface of a submount made of optically transparent material. The submount may redirect back side light emitted by the LED semiconductor light away from the LED semiconductor to increase recovery of back side light. The submount may be used with an external bulk reflecting element. The submount may itself include a reflective coating at a second surface opposite from the first surface and be mounted on a reflecting substrate. The submount may include a phosphor forming the first surface or the second surface. The first surface or the second surface may be a textured surface. An array of LED semiconductors may be mounted to the submount. The array of LED semiconductors may be disposed on the submount in an arrangement that optimizes total light output of the LED assembly.

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract: Devices and methods for their formation, including electronic assemblies having a shape memory material structure, are described. In one embodiment, a device includes a package substrate and an electronic component coupled to the package substrate. The device also includes a shape memory material structure coupled to the package substrate. In one aspect of certain embodiments, the shape memory material structure is formed from a material selected to have a martensite to austenite transition temperature in the range of 50-300 degrees Celsius. In another aspect of certain embodiments, the shape memory material structure is positioned to extend around a periphery of the electronic component. Other embodiments are described and claimed.

Abstract: A nitride-based semiconductor device including a substrate; a GaN-containing layer on the substrate; a nitride-containing layer on the GaN layer; a channel blocking layer on the nitride-containing layer, the channel blocking layer including a nitride-based semiconductor; a gate insulation layer on the channel blocking layer; and a gate electrode on the gate insulation layer.

Abstract: Disclosed is a subminiature LED element and a manufacturing method thereof. The subminiature LED element includes a first conductive semiconductor layer, an active layer formed on the first conductive semiconductor layer, and a semiconductor light emission element of a micrometer or nanometer size including a second conductive semiconductor layer formed on the active layer, wherein the outer circumference of the semiconductor light emission element is coated with an insulation film.

Abstract: The method for producing a group III nitride semiconductor crystal comprises preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing includes growing the group III nitride semiconductor so as to extend in the +C-axis direction of the seed crystal. A group III-V nitride semiconductor crystal having high quality and a large-area non-polar plane can be obtained by the method.

Abstract: A light-emitting component may include: a first electrode; an organic electroluminescent layer structure on or over the first electrode; a second translucent electrode on or over the organic electroluminescent layer structure; and a mirror layer structure on or over the second electrode, wherein the mirror layer structure has a lateral thermal conductance of at least 1*10?3 W/K.

Abstract: The embodiment of the present invention discloses a touch unit, an array substrate, a liquid crystal cell substrate and a touch display device. The touch unit comprise a plurality of touch sub-units, each of which comprising a sensor thin film transistor (TFT), an sensing capacitor, a reading induction line and a memory capacitor, the capacitance of the memory capacitor being less than that of the sensing capacitor. Due to the memory capacitor is added to stabilize the voltage of the sensor TFT, the interference of noise upon the voltage of the sensor TFT is reduced, thus effectively improving the signal stability of the touch unit.

Abstract: A semiconductor-to-metal interface with ohmic contact is provided. The interface includes a semiconductor material, a metal layer, and a silicon carbide layer disposed between the semiconductor material and the metal layer. The silicon carbide layer causes the formation of a semiconductor-to-metal interface with ohmic contact. Applications include forming a photovoltaic device with ohmic contact by disposing a layer of silicon carbide over the photovoltaic material before depositing a bottom electrode layer of metal to complete the bottom of a photovoltaic cell.

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract: A non-volatile memory device structure. The device structure includes a first electrode, a second electrode and a state change material sandwiched between the first electrode and the second electrode. In a specific embodiment, the first electrode includes a p+ type polycrystalline silicon material or a p+ type silicon germanium material. The state change material includes an n? type zinc oxide material. The second electrode includes a doped zinc oxide material. The doped zinc oxide material can be B2O3:ZnO, In2O3:ZnO, Al2O3:ZnO or Ga2O3:ZnO. The n? type zinc oxide material and the p+ type silicon material (or p+ polycrystalline silicon germanium material) further form a diode device or steering device for the non-volatile memory device.

Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.