Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.

Abstract: An electrostatic discharge (ESD) protection device is disclosed, which includes a substrate of a positive dopant type; a p-well defined in the substrate; a depletion inducing structure of a negative dopant type having a gap defined in a bottom portion thereof disposed in the p-well, and a n-channel device disposed in a planar encircled region defined by the depletion inducing structure. The well region is in connection with the substrate through the depletion inducing structure. Upon an ESD stress, the depletion inducing structure induces an expanded depletion region in the substrate under the well region, thus providing a substrate trigger mechanism that reduces the triggering voltage of the ESD protection device.

Abstract: An article, such as a light emitting device, can include a first material and a second material, wherein the first material is capable of emitting first radiation having a first emission maximum at a first wavelength, and the second material is capable of emitting second radiation in response to capturing the first radiation. The second material can have a second emission maximum at a second wavelength within the visible light spectrum. In an embodiment, the second material can be different from the first material. In another embodiment, a difference between the first wavelength and the second wavelength can be at least approximately 70 nm. Additionally, the second material can include a luminescent material having a formula of Gd3(x)Y3(1-x)Al5(y)Ga5(1-y)O12, where x is at least approximately 0.2 and no greater than approximately 0.99 and y is at least approximately 0.05 and no greater than approximately 0.99.

Abstract: A method of contact formation and resulting structure is disclosed. The method includes providing a starting semiconductor structure, the structure including a semiconductor substrate with fins coupled to the substrate, a bottom portion of the fins being surrounded by a first dielectric layer, dummy gates covering a portion of each of the fins, spacers and a cap for each dummy gate, and a lined trench between the gates extending to and exposing the first dielectric layer. The method further includes creating an epitaxy barrier of hard mask material between adjacent fins in the trench, creating N and P type epitaxial material on the fins adjacent opposite sides of the barrier, and creating sacrificial semiconductor epitaxy over the N and P type epitaxial material, such that subsequent removal thereof can be done selective to the N and P type of epitaxial material.

Abstract: MEMS devices, packaged MEMS devices, and methods of manufacture thereof are disclosed. In one embodiment, a microelectromechanical system (MEMS) device includes a first MEMS functional structure and a second MEMS functional structure. An interior region of the second MEMS functional structure has a pressure that is different than a pressure of an interior region of the first MEMS functional structure.

Abstract: Devices and methods for forming semiconductor devices with self aligned contacts for improved process windows are provided. One method includes, for instance: obtaining a wafer with at least two gates, forming partial spacers adjacent to the at least two gates, and forming at least one contact on the wafer. One intermediate semiconductor device includes, for instance: a wafer with an isolation region, at least two gates disposed on the isolation region, at least one source region disposed on the isolation region, at least one drain region disposed on the isolation region, and at least one contact positioned between the at least two gates, wherein a first portion of the at least one contact engages the at least one source region or the at least one drain region and a second portion of the at least one contact extends above a top surface of the at least two gates.

Abstract: An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.

Abstract: A field effect transistor includes a substrate, an isolation layer, a gate, a channel, drain and a source. The substrate has an active region having a rectangular area and at least one protrusion protruded from the rectangular area. The isolation layer is formed on the substrate and encircling the active region. The gate crosses the active region and is formed above a middle portion of the active region. The channel is formed in the active region directly under the gate, extends to the at least one protrusion, and divides the active region into a first section and a second section. The drain formed in the first section and the source formed in the second section.

Abstract: Embodiments of a method for forming a suspended membrane include depositing a first electrically conductive material above a sacrificial layer and within a boundary trench. The first electrically conductive material forms a corner transition portion above the boundary trench. The method further includes removing a portion of the first electrically conductive material that removes at least a portion of uneven topography of the first electrically conductive material. The method further includes depositing a second electrically conductive material. The second electrically conductive material extends beyond the boundary trench. The method further includes removing the sacrificial layer through etch openings and forming a cavity below the second electrically conductive material. The first electrically conductive material defines a portion of a sidewall boundary of the cavity.

Abstract: Optical films, and organic light-emitting display devices employing the same, include a high refractive index pattern layer including a lens pattern region and a non-pattern region alternately formed, wherein the lens pattern region includes a plurality of grooves each having a depth larger than a width thereof, and the non-pattern region has no pattern; and a low refractive index pattern layer formed of a material having a refractive index smaller than a refractive index of the high refractive index pattern layer, wherein the low refractive index pattern includes a plurality of filling portions filling the plurality of grooves.

Abstract: A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Abstract: The present disclosure relates to the field of liquid crystal display technologies, and discloses a color filter substrate and a display component. For a display component which takes a transverse electric field as a driving electric field, when a part of a black matrix of a color filter substrate is located at a non-display region, the black matrix includes a portion to be connected, and a predetermined voltage is applied to the black matrix through the portion to be connected, so as to ensure that a voltage difference between the black matrix and a pixel electrode or between the black matrix and a common electrode is small enough to be unable to drive liquid crystal molecules to deflect, thereby avoiding undesirable phenomenon such as becoming green when displaying in dark state, and improving production yield and display quality.

Abstract: The present invention relates to a variable resistance memory device and a method for forming the same. A variable resistance memory device according to the present invention includes a first electrode; a second electrode spaced apart from the first electrode; a resistance variable layer and a metal-insulator transition layer provided between the first electrode and the second electrode; and a heat barrier layer provided (i) between the first electrode and the metal-insulator transition layer, (ii) between the metal-insulator transition layer and the resistance variable layer, or (iii) between the second electrode and the metal-insulator transition layer. The present invention prevents dissipation of heat generated in the metal-insulator transition layer using a thermal boundary resistance (TBR) phenomenon, and thus current and voltage to operate the variable resistance memory device can be reduced.

Abstract: There is provided a process for forming a contained second layer over a first layer, including the steps: forming the first layer having a first surface energy; treating the first layer with a priming layer; exposing the priming layer patternwise with radiation resulting in exposed areas and unexposed areas; developing the priming layer to effectively remove the priming layer from either the exposed areas or the unexposed areas resulting in a first layer having a pattern of priming layer, wherein the pattern of priming layer has a second surface energy that is higher than the first surface energy; and forming the second layer by liquid depositions on the pattern of priming layer on the first layer. There is also provided an organic electronic device made by the process.

Abstract: An organic light-emitting display apparatus includes: a substrate; a plurality of thin film transistors on the substrate, each of the thin film transistors including an active layer, a gate electrode, and source and drain electrodes; first electrodes electrically connected to the plurality of thin film transistors, respectively, and being on respective pixels corresponding to the plurality of thin film transistors; organic layers on the first electrodes, respectively, and including light-emitting layers; auxiliary electrodes each of which is on at least a portion between adjacent organic layers of the organic layers; and a second electrode facing the first electrodes and covering the organic layers and the auxiliary electrodes.

Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; forming a second feature in a second hard mask layer formed over the patterning-target layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the first feature in the first hard mask layer within a first trench to formed a reshaped first feature; selectively removing a portion of the second feature in the second hard mask layer within a second trench to form a reshaped second feature; and transferring the reshaped first feature and the reshaped second feature to the patterning-target layer.

Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

Abstract: Embodiments of the disclosure generally provide methods of forming a silicon containing layers in TFT devices. The silicon can be used to form the active channel in a LTPS TFT or be utilized as an element in a gate dielectric layer, a passivation layer or even an etch stop layer. The silicon containing layer is deposited by a vapor deposition process whereby an inert gas, such as argon, is introduced along with the silicon precursor. The inert gas functions to drive out weak, dangling silicon-hydrogen bonds or silicon-silicon bonds so that strong silicon-silicon or silicon-oxygen bonds remain to form a substantially hydrogen free silicon containing layer.