Abstract: For fabrication of a semiconductor structure, there is set forth herein a method of fabricating a semiconductor structure, the method including forming a multilayer structure, the multilayer structure having a bulk substrate, a first layer defining an ultrathin body spaced apart from the bulk substrate, and a second layer above the first layer having material for defining a fin, and patterning the second layer to define a fin above the ultrathin body.

Abstract: A miniaturized transistor having high electrical characteristics can be provided with high yield. High performance, high reliability, and high productivity of a semiconductor device including the transistor can be achieved. The semiconductor device includes a gate electrode over an insulating surface; a base insulating film which is over the insulating surface and from which the gate electrode protrudes; a gate insulating film over the base insulating film and the gate electrode; an oxide semiconductor film over the gate insulating film; and a source electrode and a drain electrode in contact with an oxide semiconductor film. The thickness of the oxide semiconductor film is smaller than the difference between the thickness of the gate electrode and the thickness of the base insulating film.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, amounting substrate which has wiring layers containing copper, and a joining layer which is provided between the semiconductor element and the wiring layer and made of an alloy containing copper and metal other than copper, and in which a melting point of the alloy is higher than a melting point of the metal.

Abstract: A magneto-electronic device includes a first electrode, a second electrode spaced apart from the first electrode, and an electric-field-controllable magnetic tunnel junction arranged between the first electrode and the second electrode. The electric-field-controllable magnetic tunnel junction includes a first ferromagnetic layer, an insulating layer formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the insulating layer. The first and second ferromagnetic layers have respective first and second magnetic anisotropies that are alignable substantially parallel to each other in a first state and substantially antiparallel in a second state of the electric-field-controllable magnetic tunnel junction.

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Abstract: A semiconductor power device is supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate with a groove for forming an embedded gate therein, and a gate electrode embedded via a gate insulator film in the groove. A portion of the semiconductor substrate near the gate electrode is doped with a chemical element which is inactive in the semiconductor substrate.

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.

Abstract: A display device is disclosed. In one aspect, the display device includes a flexible substrate capable of being bent in a first direction and an insulating layer including a first opening pattern positioned on the flexible substrate and extending in a second direction crossing the first direction.

Abstract: An ESD device disposed on a substrate is provided. The ESD device includes a first well, a second well, a first poly-silicon region, a second poly-silicon region and a first protection layer. The first well has a first conductive type and is disposed on the substrate. The second well has a second conductive type, is disposed on the substrate and is adjacent to the first well. The first poly-silicon region is disposed on the first well. The second poly-silicon region is disposed on the second well. The first protection layer covers portions of the first well, the second well, the first poly-silicon region and the second poly-silicon region. There is no doping region in the portions of the first well and the second well which are covered by the first protection layer and between the first poly-silicon region and the second poly-silicon region.

Abstract: A method for fabricating an environmentally robust micro-wineglass gyroscope includes the steps of stacking and bonding of at least an inner glass layer and an outer glass layer to a substrate wafer; plastically deforming the inner glass layer into a mushroom-shaped structure and deforming the outer glass layer into a shield capable of extending over the inner glass layer, while leaving the inner and outer glass layers connectable at a central post location; removing the substrate layer and a portion of the inner glass layer so that a perimeter of the inner glass layer is free; and bonding the deformed inner and outer glass layers to a handle wafer. The resulting structure is an environmentally robust micro-wineglass gyroscope which has a double ended supported central post location for the mushroom-shaped structure of the inner glass layer.

Abstract: Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. Some embodiments include a memory unit which includes a memory cell and a select device electrically coupled to the memory cell. The select device has a selector region between a pair of electrodes. The selector region contains semiconductor doped with one or more of nitrogen, oxygen, germanium and carbon. The select device has current versus voltage characteristics which include snap-back voltage behavior.

Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.

Abstract: A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

Abstract: There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region. The conductive metal layer in one aspect can prevent gouging of a source/drain region during removal of materials above a source/drain region. The conductive metal layer in one aspect can be used to pattern an air spacer for reduced parasitic capacitance. The conductive metal layer in one aspect can reduce a contact resistance between a source/drain region and a contact above a source/drain region.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes proving a substrate. The substrate includes a gate stack over the substrate and source/drain regions separated by the gate stack. A first dislocation with a first pinch-off point is formed within the source/drain region with a first depth. A second dislocation with a second pinch-off point is formed within the source/drain region at a second depth. The second depth is substantial smaller than the first depth.

Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.

Abstract: A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (?m). The thickness of the semiconductor die is at least 1 ?m less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

Abstract: A robust metallization profile is formed by forming two or more layers of hard mask with different density. Multi-layer metal hard mask is helpful especially in small feature size process, for example, 50 nm and below. Lower layers have higher density. In such ways, enough process window is offered by lower layers and at the same time, round hard mask profile is offered by upper layers.