Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.

Abstract: According to one or more embodiments of the present invention, an example computer-implemented method for measuring concurrent updates in a security coprocessor includes using a first set of platform configuration registers of the security coprocessor to store and extend measurement of a code-load used during a boot sequence of a computing device. The method further includes using a second set of platform configuration registers of the security coprocessor to store and extend measurement of configuration parameters of the code-load used during the boot sequence. The method further includes using a third set of platform configuration registers of the security coprocessor to store and extend measurements of a concurrent update that changes the code-load that was used during the boot sequence.

Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.

Abstract: In a communication system for performing serial communication between a transmitting device and a receiving device, the transmitting device transmits, to the receiving device, a first data signal including at least information on a transmission clock in one frame, and transmits, to the receiving device, a second data signal including at least information on the transmission clock in one frame, during a time period from transmission of the first data signal until transmission of the first data signal in the next transmission cycle. The receiving device receives the first data signal and the second data signal transmitted from the transmitting device.

Abstract: An integrated circuit (IC) is provided. The IC includes a specific pin, a pull-down circuit and a voltage detector coupled to the specific pin, and a controller. The pull-down circuit includes a pull-down resistor corresponding to a driving voltage level, and is configured to selectively couple the pull-down resistor to the specific pin according to a control signal. The voltage detector is configured to detect the specific pin to obtain a detected voltage value. The controller is configured to determine whether the detected voltage value is the same as the driving voltage level, so as to provide the control signal. When the detected voltage value is greater or less than the driving voltage level, the controller is configured to provide the control signal to the pull-down circuit, so that the pull-down resistor is electrically separated from the specific pin.

Abstract: A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (Vdd), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.

Abstract: In an embodiment, a device includes a first high density interface in a first dilution fridge stage configured to receive a first set of transmission lines. In an embodiment, a device includes a second high density interface in a second dilution fridge stage configured to receive a second set of transmission lines. In an embodiment, a device includes a printed circuit board configured to transfer microwave signals between a first dilution fridge stage and the second dilution fridge stage, the first high density interface and the second high density interface coupled to the printed circuit board.

Abstract: Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.

Abstract: A method for switching interface device input between computing devices can begin with connecting a primary computing device to a secondary computing device using a physical connector cable using the appropriate communications port of each computing device. An interface input control program can be configured to establish a unique interface trigger that defines a user-selected series of inputs that switches the primary computing device between a first input state and a second input state. Input from the interface input devices of the primary computing device can be interpreted by a device driver. In the first input state, the input can be directed to the operating system of the primary computing device. In the second input state, the input can be redirected to the secondary computing device via the physical connector cable, which can be recognized as having originated from local interface input devices.

Abstract: A display apparatus for controlling a peripheral device and a method thereof are provided. The method may include transmitting, to a remote controller, a first turn-on signal to turn on the peripheral device; measuring a time interval between a first time when the display apparatus transmits the first turn-on signal to the remote controller and a second time when the display apparatus starts to receive content from the peripheral device in response to the first turn-on signal; and setting the measured time interval as a threshold time to determine whether the content is received from the peripheral device.

Abstract: The present technology relates to a communication device and a control method that allow variation of modes of connection between electronic devices to be increased. A transmission unit transmits a modulated signal obtained by frequency-converting a baseband signal into a signal of a frequency band higher than the baseband signal by using a predetermined carrier. A detecting unit detects a termination unit of a second electronic device having the termination unit to be detected by a first electronic device as a communication partner. A controller causes the transmission unit to transmit carriers in response to the detection of the termination unit. The present technology is applied to, for example, communication between optional electronic devices such as communication between a universal serial bus (USB) host and a USB device.

Abstract: Systems, methods, apparatuses, and architectures for storage interposers are provided herein. In one example, an apparatus includes a host connector configured to couple to one or more host systems over associated host Peripheral Component Interconnect Express (PCIe) interfaces, and PCIe switch circuitry configured to receive storage operations over the host connector that are issued by the one or more host systems. The PCIe switch circuitry is configured to monitor when ones of the storage operations correspond to an address range and responsively indicate the ones of the storage operations to a control module. The control module is configured to selectively direct delivery of the ones of the storage operations to corresponding storage areas among one or more storage devices based at least on addressing information monitored for the ones of the storage operations in the PCIe switch circuitry.

Abstract: An electronic device supporting a universal serial bus (USB) interface operating according to various embodiments includes: a housing; an opening provided in a part of the housing; a receptacle arranged in the opening and including a pin mounting portion where a plurality of first receptacle pins and a plurality of second receptacle pins are provided; and a control circuit for sensing a connection between the receptacle and an external connector, wherein, when the connection between the receptacle and the external connector is sensed, the control circuit may apply a predetermined current to any one of the plurality of first receptacle pins and the plurality of second receptacle pins. Various other embodiments are possible.

Abstract: Starting up an application is disclosed including prior to launching an application, executing startup processing associated with the application using a parent process; in response to receiving a startup command for the application, creating a child process using the parent process; and launching the application using the child process.

Abstract: A computing component is provided with physical layer logic to receive data on a physical link including a plurality of lanes, where the data is received from a particular component on one or more data lanes of the physical link. The physical layer is further to receive a stream signal on a particular one of the plurality of lanes of the physical link, where the stream signal is to identify a type of the data on the one or more data lanes, the type is one of a plurality of different types supported by the particular component, and the stream signal is encoded through voltage amplitude modulation on the particular lane.

Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a non-volatile memory (NVM) controller—to adaptively and hierarchically scale clock signals distributed to its internal components. In various examples described herein, the data storage controller is configured to downscale the internal clocks of the controller for all processing sub-blocks that are in an Active Idle state (or in similar idle states where a component is active but has no tasks to perform). When an entire hierarchy of components is idle, the clock signal applied to the entire hierarchy is downscaled. By downscaling the clock for an entire hierarchy of components, power consumed by the corresponding clock tree is also reduced. In specific examples, clock signals are downscaled by a factor of thirty-two to reduce power consumption. NVMe examples are provided herein.

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Abstract: A method includes detecting, by a first LVDC affiliated with a first host device, a request for a one-to-one communication with a second LVDC affiliated with a second host device, where data is conveyed between the LVDCs by varying loading on a bus at a frequency. The method further includes determining a desired number of channels to support the one-to-one communication based on one or more of: the first host device, the second host device, and information contained in the request, wherein the channels correspond to frequencies in a frequency band. The method further includes determining whether the desired number of channels is available for the one-to-one communication. When the desired number of channels is available for the one-to-one communication, allocating them for the one-to-one communication.

Abstract: This provides an optimized multiport NVMe controller on a single die that significantly reduces area and gate count for multipath I/O requirements over prior implementations without compromising any performance requirements. The arrangement implements minimal logic per NVMe controller as per NVMe specification requirements and implements shared logic for all common functions. This results in the desired substantial savings in gate count and area. The optimized multiport NVMe controller is used in multipath I/O-based memory subsystem where multiple hosts access Namespaces through their own dedicated queues. Illustratively, the optimized multiport NVMe controller shares common logic among NVMe controllers, providing area efficient solution for multipath I/O implementations. Shared logic across all NVMe controllers are the DMA Engine (Hardware block which handles all NVMe commands based on PRP or SGL pointers), Firmware Request Queue (FWRQ). Firmware Completion Queue (FWCQ) and DMACQ (DMA Completion Queue).

Abstract: A computing system for housing a number of storage devices includes a number of device cages, and a backplane coupled to each of the device cages to electrically couple a number of the storage devices to the computing system. The backplane includes a number of device combination signal and power interfaces located on a first side of the backplane to couple a number of the storage devices to the backplane. The backplane further includes a number of combination signal and power interfaces located on a second side of the backplane to couple the backplane to the computing system. The backplane further includes a number of signal connectors to couple the backplane to the computing system.