Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.

Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

Abstract: According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.

Abstract: A thin film transistor substrate according to an exemplary embodiment includes: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode; an oxide semiconductor disposed on the gate insulating layer; a first interlayer insulating layer disposed on the oxide semiconductor; a data line disposed on the first interlayer insulating layer; a second interlayer insulating layer disposed on the data line; a source electrode disposed on the second interlayer insulating layer and connected with the oxide semiconductor and the data line through a first contact hole through the second interlayer insulating layer; and a drain electrode disposed on the second interlayer insulating layer and connected with the semiconductor through a second contact hole through the second interlayer insulating layer.

Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.

Abstract: A semiconductor device includes a semiconductor substrate which functions as an n? drift layer, a trench IGBT formed in the front surface, an interlayer insulator film, and a metal electrode layer on the interlayer insulator film. There is a contact hole in the interlayer insulating film which has a first opening formed on the metal electrode layer side and a second opening on the semiconductor substrate side. Width w1 of the first opening on the metal electrode layer side is wider than width w2 of first opening on the semiconductor substrate side, in a direction perpendicular to the extending direction of the trench in the planar pattern of trenches. The metal electrode layer is connected to a p-type channel region and an n+ source region via the contact hole. The method of manufacturing improves the reliability of the device.

Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.

Abstract: According to one embodiment, a method of manufacturing a display device, includes preparing a first substrate formed such that a first resin layer is formed on a first support substrate, and thereafter a display element portion and a mounting portion are formed above the first resin layer and a protection layer, which extends from an end portion of the first resin layer along the mounting portion onto the first support substrate, is disposed, preparing a second substrate formed such that a second resin layer is formed on a second support substrate, attaching the first substrate and the second substrate, and mounting a flexible printed circuit board, which is in a state in which the flexible printed circuit board is opposed to the protection layer, on the mounting portion.

Abstract: Disclosed are semiconductor devices (e.g., diodes, such as PN junction diodes and PIN junction diodes, and capacitors) that have semiconductor bodies with interleaved horizontal portions. In the case of a diode, the semiconductor bodies can have different type conductivities and, optionally, can be separated by an intrinsic semiconductor layer. In the case of a capacitor, the semiconductor bodies can have the same or different type conductivities and can be separated by a dielectric layer. In any case, due to the interleaved horizontal portions, the semiconductor devices each have a relatively large active device region within a relatively small area on an integrated circuit chip. Also disclosed herein are methods of forming such semiconductor devices.

Abstract: Disclosed herein are methods of forming SiC/SiCN film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing film-precursor and an organometallic ligand transfer reagent into a processing chamber, adsorbing the silicon-containing film-precursor, the organometallic ligand transfer reagent, or both onto a surface of a semiconductor substrate under conditions whereby either or both form an adsorption-limited layer, and reacting the silicon-containing film-precursor with the organometallic ligand transfer reagent, after either or both have formed the adsorption-limited layer. The reaction results in the forming of the film layer. In some embodiments, a byproduct is also formed which contains substantially all of the metal of the organometallic ligand transfer reagent, and the methods may further include removing the byproduct from the processing chamber. Also disclosed herein are semiconductor processing apparatuses for forming SiC/SiCN film layers.

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

Abstract: Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material.

Abstract: Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an emitter and a collector of the ESD device. During an ESD event, current flows from the emitter, substantially under the dielectric isolation structure, to the collector, to protect associated circuitry. The dielectric isolation structure is formed to a depth that is less than a depth of at least one of the emitter or the collector, or doped regions thereof, thereby decreasing a length of a current path from the emitter to the collector, because the current is not obstructed by the dielectric isolation structure. Accordingly, the ESD device can carry higher current during the ESD event because the shorter current path has less resistance than a longer path that would otherwise be traveled if the dielectric isolation structure was not formed at the shallower depth.

Abstract: A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.

Abstract: A method of creating a virtual relaxed substrate includes providing a bulk semiconductor substrate, and creating a layer of strained semiconductor material on the substrate, a non-zero lattice mismatch of less than about 2% being present between the substrate and the layer of strained semiconductor material, and the layer of strained semiconductor material having a thickness of from about 50 nm to about 150 nm. The method further includes etching through the layer of strained semiconductor material and into the substrate to create shaped pillars separated by slits and sized to achieve edge effect relaxation throughout each shaped pillar, merging a top portion of the pillars with single crystal growth of epitaxial material to create a continuous surface while substantially maintaining the slits, and creating a virtual relaxed substrate by creating a layer of epitaxial composite semiconductor material over the continuous surface.

Abstract: An semiconductor structure, method of fabrication therefor, and design structure therefor is provided. A thermal grid is formed over at least a portion of a substrate. An insulating layer is formed over at least a portion of the thermal grid. A resistor is formed over at least a portion of the insulating layer. A buried interconnect is connected to the thermal grid via at least one contact. The buried interconnect is adapted to receive thermal energy from the thermal grid via the at least one contact.

Abstract: Methods of forming a fin-shaped Field Effect Transistor (FinFET) are provided. The methods may include selectively incorporating source/drain extension-region dopants into source and drain regions of a semiconductor fin, using a mask to block incorporation of the source/drain extension-region dopants into at least portions of the semiconductor fin. The methods may include removing portions of the source and drain regions of the semiconductor fin to define recesses therein. The methods may include epitaxially growing source and drain regions from the recesses in the semiconductor fin.

Abstract: A vertical tunneling field effect transistor (TFET) and method for forming a vertical tunneling field effect transistor (TFET) is disclosed. The vertical tunneling field effect transistor TFET comprises a vertical core region, a vertical source region, a vertical drain region and a gate structure. The vertical core region is extending perpendicularly from a semiconductor substrate, having a top surface, consisting of a doped outer part and a middle part. The vertical source region of semiconducting core material comprises the doped outer part of the vertical core region. The vertical drain region of semiconducting drain material comprises along its longitudinal direction a first drain part and a second drain part, the first drain part either directly surrounding said vertical source region or directly sandwiching said vertical source region between two sub-parts of said first drain part, the second drain part located directly above and in contact with the first drain part.

Abstract: A semiconductor device includes a semiconductor layer, an insulating film of silicon nitride on the semiconductor layer, source and drain electrodes formed in openings of the insulating film and in contact with the semiconductor layer, and a gate electrode formed in an opening in the insulating film that is located between the source electrode and the drain electrode and formed in contact with the semiconductor layer. The insulating film has an Si content that is uniform in a direction of thickness of the insulating film, an upper region, and a lower region. The upper region can have an oxygen concentration that is greater than that of the lower region. The upper region can be formed by exposing the surface of the insulating film to ozone or an oxygen plasma.