Patents Examined by Caleen O. Sullivan
  • Material for forming organic film, substrate for manufacturing semiconductor device, method for forming organic film, patterning process, and compound for forming organic film
    Patent number: 11500292
    Abstract: An object of the present invention is to provide: a compound containing an imide group which is not only cured under film formation conditions of inert gas as well as air and has excellent heat resistance and properties of filling and planarizing a pattern formed on a substrate, but can also form an organic underlayer film with favorable adhesion to a substrate, and a material for forming an organic film containing the compound.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: November 15, 2022
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Daisuke Kori, Keisuke Niida, Takashi Sawamura, Seiichiro Tachibana, Takeru Watanabe, Tsutomu Ogihara
  • Memory cell with top electrode via
    Patent number: 11489107
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an ILD layer over a memory device over a substrate. A hard mask structure is formed over the ILD layer and a patterning structure is formed over the hard mask structure. The hard mask structure has sidewalls defining a first opening directly over the memory device and centered along a first line perpendicular to an upper surface of the substrate. The patterning structure has sidewalls defining a second opening directly over the memory device and centered along a second line parallel to the first line. The second line is laterally offset from the first line by a non-zero distance. The ILD layer is etched below an overlap of the first and second openings to define a top electrode via hole. The top electrode via hole is with a conductive material.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Methods and apparatus for digital material deposition onto semiconductor wafers
    Patent number: 11487206
    Abstract: A microelectronic device is formed by dispensing discrete amounts of a mixture of photoresist resin and solvents from droplet-on-demand sites onto a wafer to form a first photoresist sublayer, while the wafer is at a first temperature which allows the photoresist resin to attain less than 10 percent thickness non-uniformity. The wafer moves under the droplet-on-demand sites in a first direction to form the first photoresist sublayer. A portion of the solvents in the first photoresist sublayer is removed. A second photoresist sublayer is formed on the first photoresist sublayer using the droplet-on-demand sites while the wafer is at a second temperature to attain less than 10 percent thickness non-uniformity in the combined first and second photoresist sublayers. The wafer moves under the droplet-on-demand sites in a second direction for the second photoresist sublayer, opposite from the first direction.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daniel Lee Revier, Sean Ping Chang, Benjamin Stassen Cook, Scott Robert Summerfelt
  • Semiconductor element intermediate, composition for forming metal-containing film, method of producing semiconductor element intermediate, and method of producing semiconductor element
    Patent number: 11487205
    Abstract: Provided are a semiconductor element intermediate including: a substrate and a multilayer resist layer, in which the multilayer resist layer includes a metal-containing film, and in which the metal-containing film has a content of germanium element of 20 atm % or more, or a total content of tin element, indium element, and gallium element of 1 atm % or more, as measured by X-ray photoelectric spectroscopy, and an application of the semiconductor intermediate.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 1, 2022
    Assignee: MITSUI CHEMICALS, INC.
    Inventors: Hiroko Wachi, Yasuhisa Kayaba, Hirofumi Tanaka, Kenichi Fujii
  • Secondary electron generating composition
    Patent number: 11487199
    Abstract: The present invention relates to a resist composition, especially for use in the production of electronic components via electron beam lithography. In addition to the usual base polymeric component (resist polymer), a secondary electron generator is included in resist compositions of the invention in order to promote secondary electron generation. This unique combination of components increases the exposure sensitivity of resists in a controlled fashion which facilitates the effective production of high-resolution patterned substrates (and consequential electronic components), but at much higher write speeds.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 1, 2022
    Assignee: The University of Manchester
    Inventors: Scott Lewis, Stephen Yeates, Richard Winpenny
  • Photosensitive resin composition, polymer precursor, cured film, laminate, method for producing cured film, and semiconductor device
    Patent number: 11487202
    Abstract: A photosensitive resin composition is also provided that includes a polymer precursor selected from a polyimide precursor and a polybenzoxazole precursor; a photo-radical polymerization initiator; and a solvent, in which an acid value of an acid group contained in the polymer precursor and having a neutralization point in a pH range of 7.0 to 12.0 is in a range of 2.5 to 34.0 mgKOH/g, and either the polymer precursor contains a radically polymerizable group or the photosensitive resin composition includes a radically polymerizable compound other than the polymer precursor.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 1, 2022
    Assignee: FUJIFILM Corporation
    Inventors: Takeshi Kawabata, Kenta Yoshida, Yu Iwai, Akinori Shibuya
  • Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
    Patent number: 11482530
    Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: October 25, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Composition for forming silicon-containing resist underlayer film and patterning process
    Patent number: 11480879
    Abstract: The present invention provides a resist underlayer film capable of improving LWR and CDU in a fine pattern formed by a chemically-amplified resist which uses an acid as a catalyst. A composition for forming a silicon-containing resist underlayer film, including a thermosetting silicon-containing material (Sx), a curing catalyst (Xc), and a solvent, in which a distance of diffusion of the curing catalyst (Xc) from a resist underlayer film formed from the composition for forming a silicon-containing resist underlayer film to a resist upper layer film to be formed on the resist underlayer film is 5 nm or less.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 25, 2022
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsutomu Ogihara, Tsukasa Watanabe, Yusuke Biyajima, Masahiro Kanayama
  • Memory cell with top electrode via
    Patent number: 11469372
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A top electrode via couples the top electrode to an upper interconnect wire. A first line is tangent to a first outermost sidewall of the top electrode via and a second line is tangent to an opposing second outermost sidewall of the top electrode via. The first line is oriented at a first angle with respect to a horizontal plane that is parallel to an upper surface of the substrate and the second line is oriented at a second angle with respect to the horizontal plane. The second angle is less than the first angle.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Image sensor including a first and a second isolation layer
    Patent number: 11469266
    Abstract: An image sensor is provided comprising a substrate comprising first and second surfaces opposite to each other. A first isolation layer is disposed on the substrate and forms a boundary of a sensing region. A second isolation layer is disposed at least partially in the substrate within the sensing region and has a closed line shape. A photoelectric conversion device is disposed within the closed line shape of the second isolation layer, and a color filter is disposed on the first surface of the substrate.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Eun Sub Shim
  • Heat treatment device and treatment method
    Patent number: 11469105
    Abstract: A heat treatment device includes: a heating plate that supports and heats a substrate on which a resist film is formed, and the resist film is subjected to an exposure process; a chamber that covers a processing space above the heating plate; a gas ejecting unit that ejects a processing gas from above toward the substrate on the heating plate within the chamber; a gas supply unit that supplies a gas into the chamber from below a surface of the substrate, within the chamber; and an exhaust unit that evacuates inside of the chamber through exhaust holes that are formed above the processing space and open downwards.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: October 11, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yohei Sano
  • Techniques for MRAM top electrode via connection
    Patent number: 11469269
    Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
  • Protective film forming composition having an acetal structure
    Patent number: 11460771
    Abstract: A protective film-forming composition which protects against a semiconductor wet etching solution, contains a solvent and a compound or polymer thereof containing at least one acetal structure in a molecule thereof, and forms a protective film exhibiting excellent resistance against a semiconductor wet etching solution during the lithographic process when producing semiconductors; a method for producing a resist pattern-equipped substrate which uses the protective film; and a method for producing a semiconductor device.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 4, 2022
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Takafumi Endo, Yasunobu Someya, Takahiro Kishioka
  • Memory device and manufacturing method thereof
    Patent number: 11462563
    Abstract: A memory device and a manufacturing method are provided. The method includes: forming a first conductive pattern on a substrate; forming an active structure over the first conductive pattern, wherein the active structure comprises a gate pattern, a channel pillar and a charge storage layer, the channel pillar penetrates the gate pattern and electrically connects with the first conductive pattern, and the charge storage layer is disposed between the gate pattern and the channel pillar; forming a second conductive pattern over the active structure, wherein the second conductive pattern is electrically connected with the channel pillar; and performing formation of the active structure one more time, such that the channel pillars of the active structures are vertically spaced apart from each other, and electrically connected to the second conductive pattern extending in between the channel pillars.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: October 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yong-Sheng Huang, Ming-Chyi Liu
  • Composition for resist underlayer film formation, resist underlayer film and forming method thereof, patterned substrate-producing method, and compound
    Patent number: 11454890
    Abstract: A composition for resist underlayer film formation, includes a compound represented by formula (1) and a solvent. Ar1 represents an aromatic heterocyclic group having a valency of m and having 5 to 20 ring atoms; m is an integer of 1 to 11; Ar2 is a group bonding to a carbon atom of the aromatic heteroring in Ar1 and represents an aromatic carbocyclic group having 6 to 20 ring atoms and having a valency of (n+1) or an aromatic heterocyclic group having 5 to 20 ring atoms and having a valency of (n+1); n is an integer of 0 to 12; and R1 represents a monovalent organic group having 1 to 20 carbon atoms, a hydroxy group, a halogen atom, or a nitro group.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 27, 2022
    Assignee: JSR CORPORATION
    Inventors: Naoya Nosaka, Yuushi Matsumura, Hiroki Nakatsu, Kazunori Takanashi, Hiroki Nakagawa
  • Fluoropolymer stamp fabrication method
    Patent number: 11454884
    Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: September 27, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Roman Gouk, Jean Delmas, Steven Verhaverbeke, Chintan Buch
  • Metrology apparatus and method for determining a characteristic of one or more structures on a substrate
    Patent number: 11454887
    Abstract: Disclosed is a method and associated inspection apparatus for measuring a characteristic of interest relating to a structure on a substrate. The inspection apparatus uses measurement radiation comprising a plurality of wavelengths. The method comprises performing a plurality of measurement acquisitions of said structure, each measurement acquisition being performed using measurement radiation comprising a different subset of the plurality of wavelengths, to obtain a plurality of multiplexed measurement signals. The plurality of multiplexed measurement signals are subsequently de-multiplexed into signal components according to each of said plurality of wavelengths, to obtain a plurality of de-multiplexed measurement signals which are separated according to wavelength.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 27, 2022
    Assignee: ASML Netherlands B.V.
    Inventor: Nitesh Pandey
  • EUV mask
    Patent number: 11448956
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Huang Chen, Chi-Yuan Sun, Hua-Tai Lin, Hsin-Chang Lee, Ming-Wei Chen
  • Bump bond structure for enhanced electromigration performance
    Patent number: 11450638
    Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: September 20, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dibyajat Mishra, Ashok Prabhu, Tomoko Noguchi, Luu Thanh Nguyen, Anindya Poddar, Makoto Yoshino, Hau Nguyen
  • Semiconductor device with partial EMI shielding removal using laser ablation
    Patent number: 11444035
    Abstract: A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: September 13, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoWang Koo, SungWon Cho, BongWoo Choi, JiWon Lee