Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first transistor includes a first gate structure. The first gate structure of the first transistor may include a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially disposed on the substrate. The second transistor includes a second gate structure. The second gate structure comprises a second gate structure, the second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially disposed on the substrate. The first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.

Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.

Abstract: An imprint apparatus includes: a substrate stage configured to move a substrate; an ejection unit including a plurality of nozzles and configured to eject an ejection material from the nozzles onto the substrate in synchronization with movement of the substrate stage; and a mold driving mechanism configured to drive a mold on which a pattern is formed to press down the mold onto the substrate. The imprint apparatus determines a relative ejection timing of an abnormal nozzle with respect to a normal nozzle based on ejection properties of the nozzles and a moving direction of the substrate stage, determines an ejection timing of the normal nozzle based on the determined relative ejection timing, and controls a synchronization timing of the substrate stage and the ejection unit based on the determined ejection timing of the normal nozzle.

Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.

Abstract: Provided is a method for forming an organic planarization layer. The method includes forming lithographically-patterned arrays atop a substrate; disposing a thiol-based photocurable resin on to the lithographically-patterned arrays to form a photocurable planarization layer; and curing the photocurable planarization layer to form a flat surface above the lithographically-patterned array.

Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.

Abstract: A hardmask composition, a hardmask layer, and a method of forming patterns, the composition including a solvent; and a polymer including a structural unit represented by Chemical Formula 1, wherein, in Chemical Formula 1, A is a substituted or unsubstituted dihydroxypyrene moiety, and E is a substituted or unsubstituted pyrenyl group.

Abstract: A hardmask composition, a hardmask layer, and a method of forming patterns, the composition including a solvent; and a compound represented by Chemical Formula 1, wherein, in Chemical Formula 1, A is a C6 to C30 aromatic moiety, n is an integer of 2 or more, and each B is independently a group represented by Chemical Formula 2,

Abstract: Disclosed is a method for forming patterns that can improve line width roughness (LWR) by forming a first resist material on an etch target layer, forming a second resist material including a light-shielding portion and a light-transmitting portion on the first resist material, exposing the first resist material using the light-shielding portion of the second resist material as an exposure mask, removing the second resist material, forming a first resist pattern by developing the exposed first resist material, and etching the etch target layer using the first resist pattern as an etch barrier.

Abstract: A composition for resist underlayer film formation, includes a compound represented by formula (1) and a solvent. Ar1 represents an aromatic heterocyclic group having a valency of m and having 5 to 20 ring atoms; m is an integer of 1 to 11; Ar2 is a group bonding to a carbon atom of the aromatic heteroring in Ar1 and represents an aromatic carbocyclic group having 6 to 20 ring atoms and having a valency of (n+1) or an aromatic heterocyclic group having 5 to 20 ring atoms and having a valency of (n+1); n is an integer of 0 to 12; and R1 represents a monovalent organic group having 1 to 20 carbon atoms, a hydroxy group, a halogen atom, or a nitro group.

Abstract: Techniques herein include methods for planarizing films including films used in the fabrication of semiconductor devices. Such fabrication can generate structures on a surface of a substrate, and these structures can have a spatially variable density across the surface. Planarization methods herein include depositing a first acid-labile film overtop the structures and the substrate, the first acid-labile film filling between the structures. A second acid-labile film is deposited overtop the first acid-labile film. An acid source film is deposited overtop the second acid-labile film, the acid source film including an acid generator configured to generate an acid in response to receiving radiation having a predetermined wavelength of light. A pattern of radiation is projected over the acid source film, the pattern of radiation having a spatially variable intensity at predetermined areas of the pattern of radiation.

Abstract: There are provided a plasma-curable multi-level substrate coating film-forming composition for forming a coating film having planarity on a substrate, wherein the composition can fill a pattern sufficiently.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate and a gate electrode overlying the substrate. Further, the integrated chip includes a contact layer overlies the substrate and is laterally spaced apart from the gate electrode by a spacer structure. The spacer structure may surround outermost sidewalls of the gate electrode. A hard mask structure may be arranged over the gate electrode and between portions of the spacer structure. A contact via extends through the hard mask structure and contacts the gate electrode. The integrated chip may further include a liner layer that is arranged directly between the hard mask structure and the spacer structure, wherein the liner layer is spaced apart from the gate electrode.

Abstract: A composition for forming a silicon-containing resist underlayer film contains at least: one or more compounds shown by the following general formula (P-0); and a thermally crosslinkable polysiloxane (Sx), where R100 represents divalent organic group substituted with one or more fluorine atoms; R101 and R102 each independently represent a linear, branched, or cyclic monovalent hydrocarbon group having 1 to 20 carbon atoms optionally substituted with a hetero-atom or optionally interposed by hetero-atom; R103 represents linear, branched, or cyclic divalent hydrocarbon group having 1 to 20 carbon atoms optionally substituted with a hetero-atom or optionally interposed by hetero-atom; R101 and R102, or R101 and R103, are optionally bonded to each other to form a ring with sulfur atom in the formula; and L104 represents a single bond or linear, branched, or cyclic divalent hydrocarbon group having 1 to 20 carbon atoms optionally substituted with a hetero-atom or optionally interposed by hetero-atom.

Abstract: The present invention provides a resist underlayer forming composition, which is well in heat resistance and gap filling. Further, the present invention provides methods of manufacturing a resist underlayer and semiconductor device using it. [Means for Solution] A composition comprising a allyloxy derivative having a specific group and a solvent, and methods of manufacturing a resist underlayer and semiconductor device using it.

Abstract: Disclosed is a salt represented by formula (I): wherein, in formula (I), Q1 and Q2 each independently represent a fluorine atom or the like, R1 and R2 each independently represent a hydrogen atom or the like, Z represents an integer of 0 to 6, X1 represents *—CO—O— or the like, where * represents a bonding site to C(R1)(R2) or C(Q1)(Q2), L1 represents a single bond or a saturated hydrocarbon group, and —CH2— included in the saturated hydrocarbon group may be replaced by —O—, —S—, —SO2— or —CO—, A1 represents a divalent alicyclic hydrocarbon group which may have a substituent, Ra represents a cyclic hydrocarbon group which may have a substituent, and Z+ represents an organic cation.

Abstract: New lithographic compositions for use as EUV silicon hardmask layers are provided. The present invention provides methods of fabricating microelectronic structures and the resulting structures formed thereby using EUV lithographic processes. The method involves utilizing a silicon hardmask layer immediately below the photoresist layer. The silicon hardmask layer can either be directly applied to the substrate, or it can be applied to any intermediate layer(s) that may be applied to the substrate. The preferred silicon hardmask layers are formed from spin-coatable, polymeric compositions. The inventive method improves adhesion and reduces or eliminates pattern collapse issues.

Abstract: A method for making a semiconductor apparatus includes forming a first bottom interconnect in a device area of a first dielectric layer; fabricating a device on top of the first bottom interconnect; capping the device with a first interlayer dielectric; exposing a logic area of the first dielectric layer that is adjacent to the device area by removing a portion of the first interlayer dielectric from the first dielectric layer while leaving another portion of the first interlayer dielectric that caps the device; and forming a second bottom interconnect in the logic area of the first dielectric layer. By forming the second bottom interconnect after the device fabrication and capping, damage to the device and to the second bottom interconnect is avoided.

Abstract: The present invention is a resin composition including (a) a resin, (b) an antioxidizing agent, and (d) a crosslinking agent, wherein the resin composition is characterized by the following: the resin (a) is formed of one or more kinds of resins selected from among polyimide precursor, polyamide, polyimide, polybenzoxazole, and copolymers thereof; and the crosslinking agent (d) includes a phenolic hydroxyl group in one molecule, and also includes a substituent group having a molecular weight of 40 or more at both ortho positions of the phenolic hydroxyl group. Provided is the resin composition by which obtained is a pattern-cured film that enables fine patterns to be obtained, that exhibits excellent in-plane pattern uniformity while being curable at a low temperature of 250° C. or less, and that retains high extensibility and high adhesion with metal wires even after a reliability evaluation which is an actual-use accelerated test.