Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.

Abstract: A resist composition comprising a base polymer and a salt is provided. The salt consisting of an anion derived from a carboxylic acid having an iodized or brominated hydrocarbyl group and a cation derived from a 2,5,8,9-tetraaza-1-phosphabicyclo[3.3.3]undecane, biguanide or phosphazene compound. The resist composition exerts a high sensitizing effect and an acid diffusion suppressing effect, causes no film thickness loss after development, and is improved in resolution, LWR and CDU when a pattern is formed therefrom by lithography.

Abstract: The present invention provides a material for forming an organic film, containing a compound shown by the following general formula (1), and an organic solvent, where X represents an organic group having a valency of n1 and 2 to 50 carbon atoms, n1 represents an integer of 1 to 10, and R1 represents at least one or more of the following general formulae (2) to (4). This aims to provide an organic film material for forming an organic film that has all of high filling property, high planarizing property, and excellent adhesive force to a substrate.

Abstract: A method for manufacturing a cured product pattern of a curable composition includes the steps of, in sequence, depositing a droplet of the curable composition onto a substrate; bringing a mold having an uneven pattern formed in a surface thereof into contact with the curable composition; curing the curable composition; and releasing a cured product of the curable composition from the mold. The mold has a recess having a bottom surface and a stair structure arranged to form an opening surface that becomes wider from the bottom surface toward the surface of the mold. In the contact step, the curable composition comes into contact with the stair portion after a top of the droplet comes into contact with the bottom surface.

Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

Abstract: Provided is a substrate hydrophilizing agent that improves the wettability of a substrate surface with respect to a photoresist. A substrate hydrophilizing agent of the present invention is an agent for hydrophilizing a surface of a substrate on which a pattern is formed through photolithography, and contains at least the following Component (A) and Component (B). Component (A): a water-soluble oligomer having a weight average molecular weight from 100 to less than 10000. Component (B): water. The water-soluble oligomer of Component (A) is preferably a compound represented by the following Formula (a-1): Ra1O—(C3H6O2)n—H??(a-1) (where Ra1 represents a hydrogen atom, a hydrocarbon group which may have a hydroxyl group, or an acyl group; and n is an integer from 2 to 60.

Abstract: A method of forming a pattern in a photoresist includes forming a photoresist layer over a substrate, and selectively exposing the photoresist layer to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer composition to the selectively exposed photoresist layer to form a pattern. The developer composition includes a first solvent having Hansen solubility parameters of 15<?d<25, 10<?p<25, and 6<?h<30; an acid having an acid dissociation constant, pKa, of ?15<pKa<5, or a base having a pKa of 40>pKa>9.5; and a second solvent having a dielectric constant greater than 18. The first solvent and the second solvent are different solvents.

Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.

Abstract: A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

Abstract: A stepped substrate coating composition for forming a coating film having planarity on a substrate, including: a main agent and a solvent, the main agent containing a compound (A), a compound (B), or a mixture thereof, the compound (A) having a partial structure Formula (A-1) or (A-2): and the compound (B) having at least one partial structure selected from Formulae (B-1)-(B-5), or having a partial structure including a combination of a partial structure of Formula (B-6) and a partial structure of Formula (B-7) or (B-8): where the composition is cured by photoirradiation or by heating at 30° C.-300° C.; and the amount of the main agent in the solid content of the composition is 95%-100% by mass.

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

Abstract: A composition for forming an organic film contains a polymer having a partial structure shown by the following general formula (1A) or (1B), and an organic solvent, where Ar1 and Ar2 represent a benzene ring or naphthalene ring which optionally have a substituent; X represents a single bond or methylene group; a broken line represents a bonding arm; R represents a hydrogen atom or a monovalent organic group having 1 to 20 carbon atoms; and W1 represents a hydroxyl group, an alkyloxy group having 1 to 10 carbon atoms, or an organic group having at least one aromatic ring optionally having a substituent. A composition for forming an organic film, the composition containing a polymer with high carbon content and thermosetting property as to enable high etching resistance and excellent twisting resistance; a patterning process using the composition; and a polymer suitable for the composition for forming an organic film.

Abstract: A material for forming an organic film using a polymer including an imide group for forming an organic underlayer film that cures under film-forming conditions in the air and in an inert gas, generates no by-product in heat resistance and embedding and flattening characteristics of a pattern formed on a substrate, also adhesiveness to a substrate for manufacturing a semiconductor apparatus, a method for forming an organic film, and a patterning process. The material includes (A) a polymer having a repeating unit represented by the following general formula (1A) whose terminal group is a group represented by either of the following general formulae (1B) or (1C), and (B) an organic solvent: wherein, W1 represents a tetravalent organic group, and W2 represents a divalent organic group: wherein, R1 represents any of the groups represented by the following formula (1D), and two or more of R1s may be used in combination.

Abstract: A method of forming a device includes forming a hard mask layer over an underlying layer of a substrate, forming an anti-reflective coating layer over the hard mask layer, forming a patterned resist layer over the anti-reflective coating layer, and forming a mandrel including the anti-reflective coating layer by patterning the anti-reflective coating layer using the patterned resist layer as an etch mask. The method includes forming a sidewall spacer on the mandrel including the anti-reflective coating layer, forming a freestanding spacer on the hard mask layer by removing the mandrel from the anti-reflective coating layer, and using the freestanding spacer as an etch mask, patterning the underlying layer of the substrate.

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.

Abstract: An integrated circuit includes a semiconductor substrate and a metallization structure over the semiconductor substrate. The metallization structure includes: a dielectric layer having a surface; a conductive routing structure; and an electronic circuit. Over the surface of the dielectric layer, a material is configured to set or adjust the electronic circuit.