Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. A cut structure is first formed in a stack structure. The stack structure includes interleaved initial sacrificial layers and initial insulating layers. A patterned cap material layer is formed over the stack structure. The patterned cap material layer includes an opening over the cut structure. Portions of the stack structure and the patterned cap material layer adjacent to the opening are removed to form a slit structure and an initial support structure. The initial support structure divides the slit structure into slit openings. Conductor portions are formed through the plurality of slit openings to form a support structure. A source contact is formed in each slit opening. A connection layer is formed over the source contact in each slit opening and over the support structure.

Abstract: A lithography method includes forming a bottom anti-reflective coating (BARC) layer on a substrate, wherein the BARC layer includes an organic polymer and a reactive chemical group having at least one of chelating ligands and capping monomers, wherein the reactive chemical group is bonded to the organic polymer; coating a metal-containing photoresist (MePR) layer on the BARC layer, wherein the MePR being sensitive to an extreme ultraviolet (EUV) radiation; performing a first baking process to the MePR layer and the BARC layer, thereby reacting a metal chemical structure of the MePR layer and the reactive chemical structure of the BARC layer and forming an interface layer between the MePR layer and the BARC layer; performing an exposure process using the EUV radiation to the MePR layer; and developing the MePR layer to form a patterned photoresist layer.

Abstract: Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Abstract: A light-emitting device includes a base member, conductor wiring on an upper surface of the base member, a reflective member covering the upper surfaces of the base member and the conductor wiring and having apertures to expose part of the upper surface of the base member and part of the upper surface of the conductor wiring, a plurality of light sources bonded to the part of the upper surface of the conductor wiring located in the apertures with bonding members, and a reflector that is disposed on the reflective member and includes a plurality of first surrounding portions and a plurality of second surrounding portions surrounding the first surrounding portions, which respectively surround the light sources in a plan view. Each surrounding portion has inclined lateral surfaces that widen in an upward direction. An aperture in each second surrounding portion is smaller than an aperture in each first surrounding portion in the plan view.

Abstract: Disclosed is a sol-gel imprinting ink composition comprising a sol and an additive for promoting gelation of the composition during imprinting at an imprinting temperature. The composition has a pH of 4-7 when mixed with an equal volume of deionized water and measured at 20° C. and 1 atm. The additive is the reversible reaction product of a protic acid and a proton-accepting base. The vapour pressure of the acid is higher than that of the base at the imprinting temperature such that the concentration of the base in the composition increases relative to the concentration of the acid in the composition during imprinting, resulting in basification of the composition. Further disclosed is a method of forming a patterned layer with such a sol-gel imprinting ink composition, and an optical element and an etch mask respectively including the patterned layer.

Abstract: A display device includes a substrate including a first substrate portion including a first area, a second substrate portion including a second area, and a bending area between the first substrate portion and the second substrate portion, the substrate being bendable around a bending axis that extends in a first direction, an encapsulation portion over the first substrate portion, an intermediate wiring including a first intermediate wiring portion in the first area and a second intermediate wiring portion in the second area, and a connection wiring including at least a portion in the bending area and connecting the first intermediate wiring portion to the second intermediate wiring portion.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes steps of forming a recess in the substrate; depositing an insulating layer on the substrate; forming a gate electrode on the insulating layer and partly buried in the recess; removing a portion of the insulating layer exposed through the gate electrode to form a gate dielectric; and implanting dopants in the substrate to form a source region and a drain region on either side of the gate electrode.

Abstract: A resist underlayer film forming composition contains a resin containing a unit structure represented by formula (1): [in formula (1), R1 represents a thiadiazole group which is optionally substituted with a C1-6 alkyl group optionally interrupted by a carboxy group, a C1-6 alkyl group optionally substituted with a hydroxyl group, or a C1-4 alkylthio group, and R2 represents a hydrogen atom or formula (2): (in formula (2), R1 is the same as defined above, and * represents a binding moiety)]. The resist underlayer film forming composition provides a resist underlayer film which has excellent solvent resistance, excellent optical parameters, an excellent dry etching rate, and excellent embeddability.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The memory circuit is a four transistor memory cell that includes at least the first pass gate transistor and the first pull up transistor. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact is electrically coupled to a source of the first pull up transistor. The first metal contact layout pattern extends in a second direction, overlaps a cell boundary of the memory circuit and the first active region layout pattern.

Abstract: A composition for forming an organic film contains a polymer having a partial structure shown by the following general formula (1) as a repeating unit, and an organic solvent. Each of AR1 and AR2 represents a benzene ring or naphthalene ring which optionally have a substituent; W1 represents a particular partial structure having a triple bond, and the polymer optionally contains two or more kinds of W1; and W2 represents a divalent organic group having 6 to 80 carbon atoms and at least one aromatic ring. This invention provides: a polymer curable even under film formation conditions in an inert gas and capable of forming an organic film which has not only excellent heat resistance and properties of filling and planarizing a pattern formed in a substrate, but also favorable film formability onto a substrate with less sublimation product; and a composition for forming an organic film, containing the polymer.

Abstract: A method for fabricating a semiconductor structure includes: providing a substrate and a dielectric layer on the substrate; and forming an etching mask on the dielectric layer; and etching the dielectric layer using the etching mask to form at least one opening therein. The etching mask includes: a hard mask layer, a photoresist layer, and a hexamethyldisilazane (HMDS) layer. The photoresist layer is located over the hard mask layer, and the HMDS layer is located between the hard mask layer and the photoresist layer.

Abstract: Systems and methods for custom photolithography masking via a precision dispense apparatus and process are disclosed. Methods include creating a toolpath instruction for depositing opaque onto a substrate, programming a precision dispense apparatus to execute the created toolpath instruction, and causing the precision dispense tool to deposit opaque material onto the substrate to form the photomask. The substrate may be an optically transparent plate or film or may be an electronic substrate where the opaque material is deposited directly onto a photoresist coating. Capabilities of the systems and methods disclosed herein extend to 3D substrates and custom photolithography masking, among others.

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.

Abstract: A method for exposing a photopolymerization layer comprising photopolymers includes: providing a printed circuit board, with a photopolymerization layer disposed on the top side of the printed circuit board; performing first-instance exposure on the photopolymerization layer, using a UV source and a digital micro-lens device, wherein the UV source is of a power less than 0.2 kW; stopping the first-instance exposure; covering the photopolymerization layer with a mask, with the mask having a bottom side in contact with the photopolymerization layer; and performing second-instance exposure on the photopolymerization layer, using a mercury lamp and the mask, wherein the mercury lamp is of a power greater than 5 kW.

Abstract: A semiconductor structure, and a method of making the same, includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate including n first regions extending perpendicular to the uppermost surface of the semiconductor substrate and n?1 second regions extending between and connecting each of the n first regions and parallel to the uppermost surface of the semiconductor substrate, wherein n?3.

Abstract: A method for fabricating an integrated circuit comprises forming one or more conductive features supported by pillars of a first insulating layer in a first metal layer. One or more vias are formed in a via layer, the one or more vias over and on the first metal layer and in electrical connection with ones of the one or more conductive features. Subsequent to via formation, air gaps are between adjacent ones of the one or more conductive features in the first metal layer to separate the one or more conductive features. A second insulating layer is formed over the one or more conductive features and over the one or more vias, such that the second insulating layer covers the first metal layer and the via layer while bridging over the air gaps, wherein tops the air gaps are substantially coplanar with tops of the one or more conductive features.

Abstract: A method for in-situ wave front detection within an inspection system is disclosed. The method includes generating light with a light source and directing the light to a stage-level reflective mask grating structure disposed on a mask stage. The method includes directing light reflected from the stage-level reflective structure to a detector-level mask structure disposed in a plane of a detector and then collecting, with an optical element, light reflected from the detector-level mask structure. The method includes forming a pupil image on the detector and laterally shifting the stage-level reflective mask, with the mask stage, across a grating period of the stage-level reflective mask grating structure to provide phase reconstruction for lateral shearing interferometry. The method includes selectively impinging light reflected from the optical element on the one or more sensors of the detector.

Abstract: A semiconductor photoresist composition includes an organometallic compound represented by Chemical Formula 1, an organometallic compound represented by Chemical Formula 2, and a solvent, and a method of forming patterns using the same. When the semiconductor photoresist composition is irradiated with e.g., extreme ultraviolet light, radical crosslinking between Sn-containing units may occur via Sn—O—Sn bond formation, and a photoresist polymer providing excellent sensitivity, small or reduced line edge roughness, and/or excellent resolution may be formed.

Abstract: Provided are an overlay mark, and an overlay measurement method and a semiconductor device manufacturing method using the overlay mark. Specifically, provided is an overlay mark for determining relative misalignment between two or more pattern layers or between two or more patterns separately formed in one pattern layer, the overlay mark including a first overlay mark positioned in the center, a second overlay mark positioned above and below the first overlay mark or on the left and right thereof, and a third overlay mark and a fourth overlay mark each positioned in a diagonal line with the first overlay mark in between.