Abstract: A composition for forming a silicon-containing resist underlayer film contains at least: one or more compounds shown by the following general formula (P-0); and a thermally crosslinkable polysiloxane (Sx), where R100 represents divalent organic group substituted with one or more fluorine atoms; R101 and R102 each independently represent a linear, branched, or cyclic monovalent hydrocarbon group having 1 to 20 carbon atoms optionally substituted with a hetero-atom or optionally interposed by hetero-atom; R103 represents linear, branched, or cyclic divalent hydrocarbon group having 1 to 20 carbon atoms optionally substituted with a hetero-atom or optionally interposed by hetero-atom; R101 and R102, or R101 and R103, are optionally bonded to each other to form a ring with sulfur atom in the formula; and L104 represents a single bond or linear, branched, or cyclic divalent hydrocarbon group having 1 to 20 carbon atoms optionally substituted with a hetero-atom or optionally interposed by hetero-atom.
Abstract: The present invention provides a resist underlayer forming composition, which is well in heat resistance and gap filling. Further, the present invention provides methods of manufacturing a resist underlayer and semiconductor device using it. [Means for Solution] A composition comprising a allyloxy derivative having a specific group and a solvent, and methods of manufacturing a resist underlayer and semiconductor device using it.
Abstract: Disclosed is a salt represented by formula (I): wherein, in formula (I), Q1 and Q2 each independently represent a fluorine atom or the like, R1 and R2 each independently represent a hydrogen atom or the like, Z represents an integer of 0 to 6, X1 represents *—CO—O— or the like, where * represents a bonding site to C(R1)(R2) or C(Q1)(Q2), L1 represents a single bond or a saturated hydrocarbon group, and —CH2— included in the saturated hydrocarbon group may be replaced by —O—, —S—, —SO2— or —CO—, A1 represents a divalent alicyclic hydrocarbon group which may have a substituent, Ra represents a cyclic hydrocarbon group which may have a substituent, and Z+ represents an organic cation.
Type:
Grant
Filed:
July 31, 2019
Date of Patent:
June 21, 2022
Assignee:
SUMITOMO CHEMICAL COMPANY, LIMITED
Inventors:
Tatsuro Masuyama, Takahiro Yasue, Koji Ichikawa
Abstract: New lithographic compositions for use as EUV silicon hardmask layers are provided. The present invention provides methods of fabricating microelectronic structures and the resulting structures formed thereby using EUV lithographic processes. The method involves utilizing a silicon hardmask layer immediately below the photoresist layer. The silicon hardmask layer can either be directly applied to the substrate, or it can be applied to any intermediate layer(s) that may be applied to the substrate. The preferred silicon hardmask layers are formed from spin-coatable, polymeric compositions. The inventive method improves adhesion and reduces or eliminates pattern collapse issues.
Type:
Grant
Filed:
August 21, 2020
Date of Patent:
June 14, 2022
Assignee:
Brewer Science, Inc.
Inventors:
Yichen Liang, Andrea M. Chacko, Yubao Wang, Douglas J. Guerrero
Abstract: A method for making a semiconductor apparatus includes forming a first bottom interconnect in a device area of a first dielectric layer; fabricating a device on top of the first bottom interconnect; capping the device with a first interlayer dielectric; exposing a logic area of the first dielectric layer that is adjacent to the device area by removing a portion of the first interlayer dielectric from the first dielectric layer while leaving another portion of the first interlayer dielectric that caps the device; and forming a second bottom interconnect in the logic area of the first dielectric layer. By forming the second bottom interconnect after the device fabrication and capping, damage to the device and to the second bottom interconnect is avoided.
Type:
Grant
Filed:
May 14, 2020
Date of Patent:
June 14, 2022
Assignee:
International Business Machines Corporation
Inventors:
Ashim Dutta, Saumya Sharma, Tianji Zhou, Chih-Chao Yang
Abstract: The present invention is a resin composition including (a) a resin, (b) an antioxidizing agent, and (d) a crosslinking agent, wherein the resin composition is characterized by the following: the resin (a) is formed of one or more kinds of resins selected from among polyimide precursor, polyamide, polyimide, polybenzoxazole, and copolymers thereof; and the crosslinking agent (d) includes a phenolic hydroxyl group in one molecule, and also includes a substituent group having a molecular weight of 40 or more at both ortho positions of the phenolic hydroxyl group. Provided is the resin composition by which obtained is a pattern-cured film that enables fine patterns to be obtained, that exhibits excellent in-plane pattern uniformity while being curable at a low temperature of 250° C. or less, and that retains high extensibility and high adhesion with metal wires even after a reliability evaluation which is an actual-use accelerated test.
Abstract: A patterning method and a method for manufacturing an array substrate are provided, and the patterning method includes: forming a photolithography auxiliary film and a positive photoresist film in turn on a base substrate provided with a layer to be patterned; subjecting the photolithography auxiliary film and the positive photoresist film to a photolithography process to form a photolithography auxiliary layer pattern and a positive photoresist pattern; patterning the layer to be patterned; and UV irradiating the photolithography auxiliary layer pattern and the positive photoresist pattern and then removing the photolithography auxiliary layer pattern and the positive photoresist pattern.
Abstract: An exposure apparatus for transferring a pattern of a reticle onto a wafer is provided. The exposure apparatus includes an illumination module, a reticle stage, a projection module, a wafer stage, and a control unit. The control unit is configured to calculate an alignment setting of the reticle. The wafer includes a first layer and a second layer disposed on the first layer. The first layer includes a first alignment parameter. The second layer includes a second alignment parameter. The control unit obtains a first weighting factor predetermined according to a property of the first layer, and a second weighting factor predetermined according to a property of the second layer. The alignment setting of the reticle is calculated according to the first alignment parameter, the first weighting factor, the second alignment parameter, and the second weighting factor.
Type:
Grant
Filed:
November 25, 2019
Date of Patent:
May 24, 2022
Assignee:
XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
Type:
Grant
Filed:
December 3, 2019
Date of Patent:
May 24, 2022
Assignee:
Micron Technology, Inc.
Inventors:
Jordan D. Greenlee, Lifang Xu, Rita J. Klein, Xiao Li, Everett A. McTeer
Abstract: Disclosed are methods of forming a pattern and methods of fabricating a semiconductor device. A method of fabricating a semiconductor device may include providing a substrate comprising a resist layer on the substrate and coating a compound on the resist layer to form a charge dissipation layer. The charge dissipation layer may include a conductive polymer and a metal complex.
Abstract: A method of manufacturing a conductive wire structure including following steps is provided. A conductive layer is formed on a substrate. A rectangular ring spacer is formed on the conductive layer by a self-aligned double patterning process. A patterned photoresist layer is formed. The patterned photoresist layer exposes a first portion and a second portion of the rectangular ring spacer. The first and second portions are located at two corners on a diagonal of the rectangular ring spacer. The first and second portions are removed by using the patterned photoresist layer as a mask to form a first spacer and a second spacer. The first spacer and the second spacer are L-shaped. The patterned photoresist layer is removed. A pattern of the first spacer and a pattern of the second spacer are transferred to the conductive layer to form an L-shaped first conductive wire and an L-shaped second conductive wire.
Abstract: A process for making an interconnect of a group III-V semiconductor device includes the steps of applying a positive photoresist layer and an image-reversible photoresist layer, subjecting the image-reversible photoresist and positive photoresist layers to patternwise exposure, subjecting the image-reversible photoresist layer to image reversal bake, subjecting the image-reversible photoresist and positive photoresist layers to flood exposure, subjecting the image-reversible photoresist and positive photoresist layers to development, depositing a diffusion barrier layer, depositing a copper layer, and removing the image-reversible photoresist and positive photoresist layers.
Abstract: This disclosure relates generally to a patterning structure including an underlayer and an imaging layer, as well as methods and apparatuses thereof. In particular embodiments, the underlayer provides an increase in radiation absorptivity and/or patterning performance of the imaging layer.
Type:
Grant
Filed:
January 11, 2021
Date of Patent:
April 26, 2022
Assignee:
Lam Research Corporation
Inventors:
Samantha S. H. Tan, Jun Xue, Mary Anne Manumpil, Jengyi Yu, Da Li
Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.
Type:
Grant
Filed:
March 27, 2020
Date of Patent:
April 19, 2022
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. The second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer.
Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.
Type:
Grant
Filed:
March 2, 2020
Date of Patent:
April 12, 2022
Assignee:
International Business Machines Corporation
Abstract: A composition for forming a resist underlayer film that functions as an anti-reflective coating during exposure and can be embedded in a recess having a narrow space and a high aspect ratio, and has excellent resistance to an aqueous hydrogen peroxide solution. A resist underlayer film-forming composition containing a resin, a compound of the following Formula (1a) or (1b): wherein X is carbonyl group or methylene group, 1 and m are each independently an integer of 0 to 5 and satisfy a relational expression of 3?1+m 10, and n is an integer of 2 to 5, and a solvent, wherein the compound of Formula (1a) or (1b) is contained in an amount of 0.01% by mass to 60% by mass relative to the amount of the resin.
Abstract: The present invention provides an alkali-soluble resin with which a cured film having high extensibility, reduced stress, high adhesion to a metal, and high heat resistance can be obtained, and a photosensitive resin composition containing the alkali-soluble resin, and the present invention is an alkali-soluble resin (A) including a structure represented by a general formula (1) wherein X1 represents a divalent organic group having 2 to 100 carbon atoms, Y1 and Y2 each represent a divalent to hexavalent organic group having 2 to 100 carbon atoms, X2 represents a tetravalent organic group having 2 to 100 carbon atoms, p and q each represent an integer in a range of 0 to 4, and n1 and n2 each represent an integer in a range of 5 to 100,000, wherein (I) and (II) described below are satisfied: (I) an organic group having an aliphatic chain having 8 to 30 carbon atoms is contained as X1 of the general formula (1) at a content of 30 to 70 mol % based on 100 mol % of a total of X1 and X2, and (II) an organic group h
Abstract: A light shielding film made up of a material containing one or more elements selected from silicon and tantalum and a hard mask film made up of a material containing chromium, oxygen, and carbon are laminated on a transparent substrate. The hard mask film is a single layer film having a composition gradient portion with increased oxygen content on the surface and on the neighboring region. The maximum peak for N1s in a narrow spectrum obtained via X-ray photoelectron spectroscopy analysis is the lower limit of detection or less. The portions excluding the composition gradient portion of the hard mask film have a 50 atom % or more chromium content, and the maximum peak for Cr2p in a narrow spectrum obtained via X-ray photoelectron spectroscopy analysis has a binding energy of 574 eV or less.
Abstract: Integrated chips and methods of forming lines in the same include forming a line layer on a substrate. An opening is etched into the line layer that exposes the substrate. A plug is formed in the opening. The line layer is patterned to form a line that terminates at the plug.
Type:
Grant
Filed:
January 22, 2020
Date of Patent:
March 15, 2022
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Brent Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert Robison