Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

Abstract: Disclosed herein are methods, structures, and devices for wafer scale testing of photonic integrated circuits.

Abstract: An apparatus and method perform supersonic cold-spraying to deposit N and P-type thermoelectric semiconductor, and other polycrystalline materials on other materials of varying complex shapes. The process developed has been demonstrated for bismuth and antimony telluride formulations as well as Tetrahedrite type copper sulfosalt materials. Both thick and thin layer thermoelectric semiconductor material is deposited over small or large areas to flat and highly complex shaped surfaces and will therefore help create a far greater application set for thermoelectric generator (TEG) systems. This process when combined with other manufacturing processes allows the total additive manufacturing of complete thermoelectric generator based waste heat recovery systems. The processes also directly apply to both thermoelectric cooler (TEC) systems, thermopile devices, and other polycrystalline functional material applications.

Abstract: Techniques herein include systems and methods for dispensing liquids on a substrate with real-time coverage control and removal control. Techniques also encompass quality control of dispense systems. Systems and methods enable visual examination of liquids progressing on a surface of a substrate. This includes capturing and/or examining stroboscopic images of movement of a given liquid on a working surface of a substrate, and then generating feedback data for modifying a corresponding dispense. Dispenses can be modified by increasing/decreasing a dispense rate and increasing/decreasing a rotational velocity of a substrate. Feedback can be generated by automated and/or manual analysis of real time progression as well as post-process analysis of collections of images.

Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having conductive bumps disposed on a first surface; forming a first adhesion layer and a first carrier board; thinning the wafer; forming a first insulating layer; forming a second adhesion layer and a second carrier board; heating the first adhesion layer to a first temperature to remove the first carrier board and the first adhesion layer; forming trenches; forming a third adhesion layer and a third carrier board; heating the second adhesion layer to a second temperature to remove the second carrier board and the second adhesion layer; forming a second insulating layer filling the trenches; heating the third adhesion layer to a third temperature to remove the third carrier board and the third adhesion layer; and dicing the first insulating layer and the second insulating layer along each trench.

Abstract: A manufacturing method of an organic electronic device of the present invention, includes: a removing step of removing a volatile component from a flexible base material; a fixing step of fixing the flexible base material onto a support substrate via an adhesive layer; and a forming step of forming a device main body sequentially including a first electrode layer, at least one organic functional layer, and a second electrode layer on the flexible base material that is fixed onto the support substrate, on a side opposite to the support substrate, in this order, in which a vapor pressure of the volatile component is greater than or equal to 101325 Pa within a temperature range from 20° C. to a melting point of a parent resin of the flexible base material.

Abstract: Embodiments are disclosed for a method to process microelectronic workpieces including forming a metal hard mask layer including ruthenium (Ru MHM layer) over one or more underlying layers on a substrate for a microelectronic workpiece, etching the Ru MHM layer to provide a patterned Ru MHM layer, and etching the one or more underlying layers using the patterned Ru MHM layer as a mask to protect portion of the one or more underlying layers. For one embodiment, the Ru MHM layer is a material including 95 percent or more of ruthenium (Ru). For another embodiment, the Ru MHM layer is a material including 70 percent or more of ruthenium (Ru). Further, the Ru MHM layer preferably has a selectivity of 10 or greater with respect to a next underlying layer adjacent to the Ru MHM layer, such as a SiN hard mask layer.

Abstract: A laser irradiation apparatus includes a laser generation device, a levitation unit to levitate an object to which the laser light is applied, and a conveyance unit to convey the levitated object. The conveyance unit includes a holding mechanism for holding the object by absorption, and a moving mechanism for moving the holding mechanism in a conveyance direction. The holding mechanism includes a base including a plurality of through holes, a plurality of pipes respectively connected to the through holes, a vacuum generation device configured to evacuate air from the f pipes, and a plurality of absorption assistance valves each disposed in the middle of a respective one of the pipes, each of the plurality of absorption assistance valves being configured to be closed when a flow rate of a gas flowing into the pipe through the through hole becomes equal to or higher than a threshold.

Abstract: The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate.

Abstract: The present disclosure provides a display substrate, which includes a base substrate and a light emitting element layer, which is on a side of the base substrate and includes a pixel defining layer and a plurality of light emitting elements. The pixel defining layer includes a plurality of pixel openings and a plurality of light transmission holes, and the plurality of light emitting elements are in the plurality of pixel openings, respectively. Each of the plurality of light transmission holes penetrates through the pixel defining layer in a thickness direction of the pixel defining layer. Portions of the pixel defining layer not provided with the plurality of pixel openings or the plurality of light transmission holes are opaque light shields, and a portion of the display substrate overlapping each of the plurality of light transmission holes in the thickness direction is light transmissive.

Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having an upper surface and a lower surface opposite thereto, in which the wafer comprises a plurality of conductive pads disposed on the upper surface; dicing the upper surface of the wafer to form a plurality of trenches; forming a patterned photoresist layer on the upper surface and in the trenches; forming a plurality of conductive bumps disposed correspondingly on the conductive pads; thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface; forming an insulating layer under the lower surface; and dicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages.

Abstract: An integrated circuit device is provided. The integrated circuit device includes a semiconductor substrate having a circuit area and a guarding area surrounding the circuit area. A guarding structure is formed in the guarding area, and includes a diffusion region in the semiconductor substrate. The guarding structure also includes a gate stack disposed on the semiconductor substrate and positioned adjacent to the diffusion region. The guarding structure further includes a guarding layer disposed on the gate stack. The gate stack extends in a first direction while the guarding layer extends in a second direction that is different from the first direction. The guarding layer is electrically insulated from the diffusion region. Thus, an integrated circuit device including a guarding structure with several capacitors is provided.

Abstract: Electronic devices and methods with a barrier layer and methods of forming the barrier layer are described. A substrate can be exposed to a metal precursor (e.g., a tantalum precursor), a reactant (e.g., ammonia) and an optional plasma to form a first thickness of the barrier layer. An optional aluminum film can be formed on the first barrier layer and a second barrier layer is formed on the first barrier layer to form barrier layer with an aluminum inter-layer.

Abstract: An organic EL device includes a pair of electrodes and an organic compound layer between pair of electrodes. The organic compound layer includes an emitting layer including a first material, a second material and a third material, in which singlet energy EgS(H) of the first material, singlet energy EgS(H2) of the second material, and singlet energy EgS(D) of the third material satisfy a specific relationship.

Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

Abstract: Methods of making an integrated circuit for a single-molecule nucleic-acid assay platform. In one example, the method includes adhering a carbon nanotube to a surface of a transfer film, the transfer film comprising gold or a polymer; placing the surface of the transfer film on a CMOS integrated circuit; releasing the carbon nanotube from the transfer film; and forming a pair of post-processed electrodes proximate opposing ends of the carbon nanotube, the post-processed electrodes electrically connecting the carbon nanotube to the CMOS integrated circuit. The method can also include exposing the carbon nanotube to a diazonium salt solution to form a point defect on a portion of the carbon nanotube.

Abstract: A method is described for configuring a custom server processor including a base die and related components. For example, one embodiment includes: providing a secure website to a user for configuring a custom server processor, the secure website including a graphical user interface (GUI); providing a first graphical element from which a user is to select a base die and an associated package; providing a second graphical element including a plurality of building block options selectable by the user to populate landing slots in the selected base die; providing a third graphical element including a visual representation of a user configuration that includes one or more building blocks selected by the user in the second graphical element and arranged on the base die selected by the user in the first graphical element; and performing a verification of the user configuration.

Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.