Abstract: Embodiments of the disclosed subject matter may provide a wearable device that includes an organic light emitting diode (OLED) light source to output light. At least one emissive layer of the OLED light source of the wearable device may have a plurality of segments that are independently controllable to output the light at a duty cycle of less than 100%. The OLED light source of the wearable device may be encapsulated.

Abstract: A composition includes a product of a condensation reaction between a thermal cross-linking agent and a product of hydrolysis and condensation polymerization of a compound represented by Chemical Formula 1.

Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.

Abstract: An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.

Abstract: A display device includes a substrate including a trench portion. The substrate includes a display area and a peripheral area adjacent to the display area. The display area includes a first display area and a second display area arranged with the trench portion therebetween to display an image. A thin-film transistor and a display element are each arranged in the display area. A built-in circuit portion is over the peripheral area and is adjacent to the trench portion. A first wiring is in the first display area and a second wiring is in the second display area. A connecting wiring connects the first wiring to the second wiring and overlaps the built-in circuit portion.

Abstract: A foldable display panel is provided. The foldable display panel includes a foldable area and two non-foldable areas. The foldable display panel further includes at least two pixel units. Each of the pixel units includes three sub-pixels. A pattern of the sub-pixel in the foldable area is elliptical or is curved quadrilateral. A pattern of the sub-pixel in the non-foldable area is a rhombus. An ability of the sub-pixels located in the foldable area 100 to withstand stress during a bending process is enhanced. Detachment of an electroluminescent layer or a thin film encapsulation layer located in the foldable area is prevented, thereby a reliability of a display device is ensured and a quality of the product is improved.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: Provided herein may be a method of manufacturing a semiconductor device including the step of replacing sacrificial layers of a stack with line patterns through slits that pass through the stack and have different depths.

Abstract: A method of forming a pattern includes forming a lower layer on a substrate, forming a mask pattern on the lower layer, the mask pattern extending in a first direction parallel to a top surface of the substrate, and performing an etching process using an ion beam on the substrate, such that the ion beam is irradiated in parallel to a plane defined by the first direction and a direction perpendicular to the top surface of the substrate, and is irradiated at a tilt angle with respect to the top surface of the substrate, wherein performing the etching process includes adjusting the tilt angle of the ion beam to selectively etch the lower layer or the mask pattern.

Abstract: Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.

Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.

Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.

Abstract: A plasma sputtering device including one or a plurality of plasma generating devices each including an insulating tube having an expanding inner diameter and having a gas injection port formed in an end portion or a side portion thereof, a first electromagnet or a permanent magnet group which can apply a static magnetic field, and a high frequency antenna; a second electromagnet which is disposed in a region downstream of the plasma generating device(s) and which can form a curved magnetic force line structure; a target mechanism which includes a permanent magnet embedded therein and a cooling mechanism and which can apply a DC or high frequency voltage; a substrate stage facing the target mechanism; a second permanent magnet group around the substrate stage; and a heat insulating mechanism between a target material and the target mechanism.

Abstract: A method and apparatus for of improving processing results in a processing chamber by orienting a substrate support relative to a surface within the processing chamber. The method comprising orienting a supporting surface of a substrate support in a first orientation relative to an output surface of a showerhead, where the first orientation of the supporting surface relative to the output surface is not coplanar, and depositing a first layer of material on a substrate disposed on the supporting surface that is oriented in the first orientation.

Abstract: Techniques are provided for making a funnel-shaped nozzle in a substrate. The process can include forming a first opening having a first width in a top layer of a substrate, forming a patterned layer of photoresist on the top surface of the substrate, the patterned layer of photoresist including a second opening, the second opening having a second width larger than the first width, reflowing the patterned layer of photoresist to form curved side surfaces terminating on the top surface of the substrate, etching a second layer of the substrate through the first opening in the top layer of the substrate to form a straight-walled recess, the straight-walled recess having the first width and a side surface substantially perpendicular to the top surface of the semiconductor substrate.

Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

Abstract: A display panel and a method of manufacturing the same are provided. The display panel includes a substrate and an electrode layer. The electrode layer is disposed on the substrate. The electrode layer is provided with a first defect seat and a transparent conductive patch layer. The transparent conductive patch layer overlies the first defect seat.

Abstract: In some embodiments, the present disclosure relates to an image sensor, including a first photodiode and a second photodiode disposed in a semiconductor substrate. A floating diffusion node is disposed along a frontside of the semiconductor substrate and between the first and second photodiodes. A partial backside deep trench isolation (BDTI) structure is disposed within the semiconductor substrate and between the first and second photodiodes. The partial BDTI extends from a backside of the semiconductor substrate and is spaced from the floating diffusion node. A full BDTI structure extends from the backside of the semiconductor substrate to the frontside of the semiconductor substrate.

Abstract: A method of reconstructing a characteristic of a structure formed on a substrate by a lithographic process, and an associated metrology apparatus. The method includes combining measured values of a first parameter associated with the lithographic process to obtain an estimated value of the first parameter; and reconstructing at least a second parameter associated with the characteristic of the structure using the estimated value of the first parameter and a measurement of the structure. The combining may involve modeling a variation of the first parameter to obtain a parameter model or fingerprint of the first parameter.

Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.