Patents Examined by Caridad Everhart
  • Display device
    Patent number: 10916728
    Abstract: A display device includes: a substrate including a display area and a non-display area around the display area; a light-emitting element disposed in the display area; an encapsulating layer sealing the light-emitting element; and a dam disposed in the non-display area. The dam includes a first layer and a second layer on the first layer, the first layer includes a first portion with a first height and a second portion with a second height that is less than the first height, and the second layer covers a lateral surface of the first portion.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 9, 2021
    Inventors: Gwui-Hyun Park, Jin Seock Kim, Pil Soon Hong, Chui Won Park
  • OLED light emitting device, preparation method thereof and display device
    Patent number: 10916606
    Abstract: The present disclosure provides an OLED light emitting device including a plurality of pixel defining structures disposed on a substrate, the plurality of pixel defining structures include a substrate layer and a plurality of particles randomly distributed in the substrate layer, the particles are capable of scattering light incident thereon, and the substrate layer of the pixel defining structures has a non-uniform density.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 9, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hao Gao, Yansong Li
  • Method of multiple gate oxide forming with hard mask
    Patent number: 10916438
    Abstract: Methods for fabricating an integrated circuit having a plurality of gate dielectrics. The methods are provided to include: forming one or more isolation trenches and a first active region and a second active region in a substrate; depositing hard mask material on the substrate; removing a first portion of the hard mask material over the first active region; forming a first oxide layer having a first thickness over the first active region; removing a second portion of the hard mask material over the second active region; and forming a second oxide layer having a second thickness over the first and second active regions such that a thickness of oxide formed over the first active region comprises a sum of the thickness of the first oxide layer and the second oxide layer, and a thickness of oxide formed over the second active region comprises the second thickness.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: February 9, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Maxim Klebanov, Sundar Chetlur, James McClay
  • Method of forming gate spacer for nanowire FET device
    Patent number: 10916637
    Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: February 9, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton deVilliers
  • Method for manufacturing magnetic memory element with post pillar formation annealing
    Patent number: 10916696
    Abstract: A method for manufacturing a magnetic memory element structure using a Ru hard mask and a post pillar thermal annealing process. A Ru hard mask is formed over a plurality of memory element layers and an ion milling is performed to transfer the image of the Ru hard mask onto the underlying memory element layers. A high-angle ion milling an be performed to remove any redeposited material from the sides of the memory element layers, and a non-magnetic, dielectric material can be deposited. A thermal annealing process can then be performed to repair any damage caused by the previously performed ion milling processes.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 9, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Mustafa Pinarbasi, Pradeep Manandhar, Jorge Vasquez, Bartlomiej Adam Kardasz, Thomas D. Boone
  • Protective member forming apparatus
    Patent number: 10916459
    Abstract: A holding table for holding a wafer includes plural pins, and a wafer holding surface includes the tips of the plural pins. Therefore, small dust enters between the pins and thus is less readily left between the wafer holding surface and the wafer. Therefore, when the wafer is sucked and held, a gap is less readily made between the wafer holding surface and the wafer. Thus, the occurrence of the situation in which the wafer is held in a waving state is suppressed. For this reason, when a liquid resin is pushed to spread over the lower surface of the wafer, an air bubble enters less readily between the liquid resin and the wafer. This can suppress entry of the air bubble in a protective member obtained by curing the liquid resin.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 9, 2021
    Assignee: DISCO CORPORATION
    Inventor: Shinichi Namioka
  • Three-dimensional memory device including electrically conductive layers with molybdenum-containing liners
    Patent number: 10916504
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 9, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yusuke Mukae, Naoki Takeguchi, Kensuke Yamaguchi, Raghuveer S. Makala, Yujin Terasawa
  • Method of reducing residual contamination in singulated semiconductor die
    Patent number: 10916474
    Abstract: A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 9, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Method of fabricating layered structure
    Patent number: 10903069
    Abstract: A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: January 26, 2021
    Assignee: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD.
    Inventors: Chung Hon Lam, Hao Ren Zhuang, Kuo-Feng Lo, Yen Yu Hsu
  • Method for manufacturing a magnetic memory element using Ru and diamond like carbon hard masks
    Patent number: 10903002
    Abstract: A method for manufacturing a magnetic memory element array that includes the use of a Ru hard mask layer and a diamond like carbon hard mask layer formed over the Ru hard mask layer. A plurality of magnetic memory element layers are deposited over a wafer and a Ru hard mask layer is deposited over the plurality of memory element layers. A layer of diamond like carbon is deposited over the Ru hard mask layer, and a photoresist mask is formed over the layer of diamond like carbon. A reactive ion etching is then performed to transfer the image of the photoresist mask onto the diamond like carbon mask, and an ion milling is performed to transfer the image of the patterned diamond like carbon mask onto the underlying Ru hard mask and memory element layers. The diamond like carbon mask can then be removed by reactive ion etching.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 26, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Elizabeth A. Dobisz, Thomas D. Boone
  • Substrate processing system and substrate processing apparatus
    Patent number: 10903098
    Abstract: There is provided a technique that includes a first controller configured to acquire event data generated at a time of transferring a substrate and alarm data generated at a time of occurrence of a transfer error, a recorder configured to, while recording a transfer operation of the substrate as first image data, record the transfer operation of the substrate as second image data having a higher resolution than the first image data, a second controller configured to store the first image data in a first memory based on the event data, and store the second image data in a second memory based on the alarm data, and an operating controller configured to display at least the first image data and the second image data. The second controller displays both the first image data and the second image data on a same screen.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 26, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Akihiko Yoneda, Kazuhide Asai, Tetsuyuki Maeda, Naoya Miyashita, Nobuyuki Miyakawa, Tadashi Okazaki, Hideo Yanase
  • Electro-optical device, method for manufacturing electro-optical device, and electronic apparatus
    Patent number: 10896999
    Abstract: There is provided an electro-optical device including a light-emitting layer that has a first light-emitting element and a second light-emitting element which are adjacent to each other and a color filter layer that has a first color filter provided corresponding to the first light-emitting element and a second color filter provided corresponding to the second light-emitting element, in which an inter-element distance between the first light-emitting element and the second light-emitting element is 1.5 ?m or less, and a thickness of layer between the light-emitting layer and the color filter layer is 6 times or less the inter-element distance.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: January 19, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takeshi Koshihara
  • Fin field effect transistor having crystalline titanium germanosilicide stressor layer
    Patent number: 10892365
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Multivalent oxide cap for analog switching resistive memory
    Patent number: 10892408
    Abstract: A resistive random access memory (RRAM), including a first electrode, a base oxide being connected to the first electrode, and a multivalent oxide being connected to the base oxide layer. The multivalent oxide switches oxidative states.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • Die interconnect structures and methods
    Patent number: 10892225
    Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun
  • Flexible electroluminescence display
    Patent number: 10886489
    Abstract: Disclosed is an electroluminescence display device. The electroluminescence display device includes a flexible substrate, a first metal layer, an inorganic material layer, a recessed portion, a second metal layer, and an organic material layer. The flexible substrate has a bending axis. The first metal layer is disposed on the flexible substrate to be parallel with the bending axis. The inorganic material layer is stacked on the first metal layer. The recessed portion is disposed in the inorganic material layer to be parallel to the bending axis and exposes the first metal layer. The second metal layer extends in parallel to the bending axis, covers the recessed portion, and is in contact with the first metal layer. The organic material layer covers the inorganic material layer and the second metal layer.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: January 5, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: MinJic Lee, HongSik Kim, Yeseul Han, JeongOk Jo
  • Display device including a crack detection line
    Patent number: 10886493
    Abstract: A display device includes a substrate including a display area and a non-display area. The display device further includes a plurality of pixels in the display area of the substrate. The display device additionally includes a plurality of gate lines and a plurality of data lines respectively connected to the plurality of pixels. The display device further includes a plurality of insulative step portions disposed in the non-display area of the substrate and arranged in a first direction parallel to sides of the display area. The display device further includes a crack detection line in the non-display area and extending primarily in the first direction. The crack detection line includes a first portion which does not overlap the plurality of insulative step portions, and a second portion overlapping each of the insulative step portions.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Keun Soo Lee, Neung Ho Cho
  • Integrated light-emitting pixel arrays based devices by bonding
    Patent number: 10884560
    Abstract: Integrated active-matrix light emitting pixel arrays based displays are provided. An example integrated device includes a backplane including pixel circuits conductively coupled to an array of light-emitting elements through intermediate conductive layers to form an array of active-matrix light-emitting pixels and a transparent conductive layer on the array of the light-emitting elements. Each of the light-emitting elements includes one or more quantum well semiconductor layers between a first contact electrode and a second contact electrode, and the first contact electrodes of the light-emitting elements is respectively bonded and conductively coupled to the pixel circuits in the backplane via the respective intermediate conductive layers.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 5, 2021
    Inventor: Shaoher Pan
  • Method for manufacturing semiconductor device and method for evaluating semiconductor device
    Patent number: 10886129
    Abstract: A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 5, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Tadashi Nakasugi, Hiroshi Takeno, Katsuyoshi Suzuki
  • Cover for an electronic device and method of fabrication
    Patent number: 10886210
    Abstract: A cover for an electronic device includes a support body having a through-passage. An optical element which allows light to pass is mounted on said support body in a position extending across the through-passage. A surface of the optical element includes an electrically-conducting track configured as a security detection element. At least two electrical connection leads are rigidly attached to the support body and include first uncovered portions internal to the support body and electrically connected to spaced apart locations on the electrically-conducting track. The at least two electrical connection leads further including second uncovered portions external to said support body. The cover is mounted on a support plate carrying an electronic chip situated in the through-passage at a distance from the optical element.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 5, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Romain Coffy