Abstract: A MIS transistor comprises a semiconductor substrate having a first conductivity type, a source region and a drain region disposed in the semiconductor substrate in spaced-apart relation from one another and having a second conductivity type, and an insulating film disposed on the surface of the semiconductor substrate. A gate electrode is disposed on the insulating film between the source region and the drain region. A diffused region having the first conductivity type is disposed in the semiconductor substrate and in contact with the source region. An oxide film is disposed on the diffused region.

Abstract: A semiconductor device includes a flat, square n-type diffusion layer, a p-type channel stopper region, and an electrode. The n-type diffusion layer is formed to be isolated in a check element region of a p-type semiconductor substrate or a p-type well covered with a field oxide film and having circuit element regions and the check element region sandwiched therebetween. The p-type channel stopper region is formed to contact at least one side of the n-type diffusion layer. The electrode is extracted from the n-type diffusion layer through a contact hole. The n-type diffusion layer, the p-type channel stopper region, and the electrode constitute the check element for checking a state of the p-type channel stopper region by measuring a junction breakdown voltage of the n-type diffusion layer.

Abstract: The object of the invention is a field-effect transistor comprising a drain (D) and a source (S) and a gate (G) with a determined width (W) and length (L), equipped with means (G1-G2) for generating a voltage distribution on the gate in direction of its width. The gate comprises a first end in direction of its width and a second end essentially opposite to the first end, and that a first gate contact (G1) is arranged at the first end for providing a first voltage (V.sub.G1) to the first end, and a second gate contact (G2) is arranged at the second end for providing a second voltage (V.sub.G2) to the second end, for generating a voltage distribution on the gate in direction of its width with the help of a difference voltage (V.sub.G1 -V.sub.G2) between the first (G1) and the second (G2) gate contact. On the basis of the first (V.sub.G1) and second (V.sub.

Abstract: A thin film transistor of this invention includes: a source and drain regions formed on an insulating base region; and a conductive layer connected to the source and drain regions. The conductive layer has a layered structure of an Al-containing metal film and an N-containing Mo film.

Abstract: A semiconductor device has trenches formed on the surface of a semiconductor. The device passes a main current through a channel formed between the trenches and controls the main current with the use of gate electrodes buried in the trenches. The main current directly controlled by the gate electrodes flows in parallel with the surface of the semiconductor and is distributed vertically to the surface of the semiconductor. The width W of the channel is freely increased without regard to the surface area of the semiconductor.

Abstract: This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.

Abstract: A semiconductor photosensitive element comprises first and second photosensitive regions. The first photosensitive region is different from the second photosensitive region in its structure and thereby the first photosensitive region has photoelectric conversion characteristic and frequency characteristic which are different from those of the second photosensitive region.

Abstract: A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Abstract: Pulse shaped voltage of 5V is applied to a source region 3 at initial phase of erase by a pull back voltage generator 13 connected to the sources region 3. Then, the pulse shaped voltages of 10V and 12V increased under stepwise bases are applied to source region 3 with progress of erasion. Generation of hot-holes at the initial phase of data erasion can be prevented because difference in voltage between the floating gate electrode 5 and source region 3 is decreased. Value of the pulse shaped voltage thus applied is increased for the difference occurred between the floating gate electrode 5 and source region 3 when erasion is in much progress. Thus, it is possible to pull out the stored electrons from the floating gate electrode 5 until the threshold voltages can be set at predetermined values. So that, degradation of characteristics of a gate oxidation layer caused by hot-holes generated with erasion can be prevented.

Abstract: A superconductive junction (10) comprises a first track (22) of YBa.sub.2 Cu.sub.3 O.sub.7 surmounted by a second track (28) also of YBa.sub.2 Cu.sub.3 O.sub.7. An interconnect (26) in the form of a superconductive mesa electrically connects the first track to the second track and acts as a microbridge. When cooled below a critical temperature, the junction (10) shows Josephson-like behaviour. A non-superconductive layer (24) of PrBa.sub.2 Cu.sub.3 O.sub.7 separates the first track and the second track, with the interconnect extending through the PrBa.sub.2 Cu.sub.3 O.sub.7 layer in the form of an island. The junction (10) is fabricated by electron beam evaporation, optical lithography, and ion beam milling.

Abstract: A bipolar semiconductor integrated circuit has a pnp transistor through which a DC power is supplied from an external DC power to various elements of the bipolar IC and a constant current circuit for turning the pnp transistor on and regulating the base current of the pnp transistor to a constant level causing operation in the saturation range of the pnp transistor.

Abstract: Into an amorphous silicon film, catalyst elements for accelerating the crystallization are introduced. After patterning the amorphous silicon films in which the catalyst elements have been introduced into an island pattern, a heat treatment for the crystallization is conducted. Thus, the introduced catalyst elements efficiently diffuse only inside the island-patterned amorphous silicon films. As a result, a high-quality crystalline silicon film, having the crystal growth direction aligned in one direction and having no grain boundaries, is obtained. Using the thus formed crystalline silicon film, semiconductor devices having a high performance and stable characteristics are fabricated efficiently over the entire substrate, irrespective of the size of the devices.

Abstract: A thin film transistor which includes an insulation base, first and second gate electrodes, first and second insulation layers, an active layer of semiconductor material, a source electrode and a drain electrode, in which a lateral length of the first gate electrode is narrower than a lateral length of the second gate electrode. Also, the first gate is electrically insulated from the active layer of semiconductor material by the first insulation layer so that the drain current saturates in a high drain voltage region.

Abstract: A card type semiconductor device includes a main circuit board and a first sub-circuit-board equipped with a main memory. The main circuit board is connected to the first sub-circuit-board through an FPC. A first TCP equipped with the CPU and a second TCP equipped with the I/O sub-system chip are mounted on the top and bottom surfaces of the main circuit board. The first and second TCPs are mounted to directly oppose each other. The card type semiconductor device is used as a card type computer. The main circuit board and the sub-circuit-board face each other by bending the FPC and enclosing the main circuit board and the sub-circuit-board in a card-shaped thin housing. The card type semiconductor device achieves a high density packaging in a small form factor.

Abstract: A field effect transistor structure having a first type conductivity semiconductor body disposed on an insulator and having formed in different regions of the semiconductor, a source region and a drain region of the opposite type conductivity to the first type, a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions, and a Schottky diode contact region between the semiconductor body and one of the source or the drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 volts, between the semiconductor body and one of the source or the drain regions.

Abstract: A micro-switch having a flexible conductive membrane which is moved by an external force, such as pressure from an air flow, to establish a connection between contact pads. The conductive membrane is stretched over one or more spacer pads to introduce deformation in the conductive membrane, thereby improving the accuracy and repeatability of the micro-switch. The spacing between the contact pads and the conductive membrane is precisely controlled by controlling the height difference between the spacer pads and the conductive pads. This height difference is determined by one or more precisely controlled etch operations.

Abstract: A semiconductor device provide with an ESD circuit including three active regions and element isolating regions formed on a semiconductor substrate in such a manner that the active regions are isolated from one another by the element isolating regions, source/drain diffusion regions respectively formed at the active regions, a first interlayer insulating film formed on the semiconductor substrate in such a manner that it covers the active regions and element isolating regions while being provided with first contact holes for exposing the diffusion regions, first lines formed on the first interlayer insulating film in such a manner that they are electrically connected to the diffusion regions via the first contact holes, respectively, a second interlayer insulating film formed over the entire exposed surface of the resulting structure obtained after the formation of the first line in such a manner that it has second contact holes for exposing the first line disposed over a central one of the active regions, an

Abstract: An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by bonding of integrated circuit chips into a chip stack and bonding the chip stack onto a substrate such as a chip, board, module or another integrated circuit by forming a solder or conductive adhesive bond between a bonding/contact pad on the substrate and a metallization feature extending at least on limited opposing areas of major surfaces of the chip and across the edge of the chip. Thickness of the metallization feature and bonding material provides a "stand-off" between chips allowing improved heat dissipation by fluid flow, conduction through a viscous thermally conducting material and/or a heat sink disposed between chips in the stack.

Abstract: A method of manufacturing a semiconductor memory device having a plurality of memory cells arranged in matrix includes forming a first masking layer on a semiconductor substrate of a first conductivity type and patterning the first masking layer to form a plurality of parallel strips which extend in first direction. A second masking layer is formed on the patterned first masking layer and the second masking layer is patterned to form a plurality of parallel strips which extend in a second direction perpendicular to the first direction. First impurities of a second conductivity type are implanted into the semiconductor substrate, using the patterned first and second masking layers as a mask, to form impurity regions of the second conductivity type. The patterned second masking layer is then removed and an insulating film is formed in the spaces between the parallel strips of the patterned first masking layer for isolating element regions on the semiconductor substrate.

Abstract: A semiconductor memory device has memory cells including a capacitor for storing data, and a transistor for inputting a ground voltage at its substrate and for selectively connecting the capacitor to a bit line. The device also has sense amplifiers that sense and amplify data that is transferred from the memory cells to the bit line. The device further has a first internal voltage supply circuit that generates a first internal voltage and supplies it to the sense amplifiers. The device also has a PMOS transistor for switching the first internal voltage from the first internal voltage supply circuit to the sense amplifiers, a second internal voltage supply circuit that generates a second internal voltage and supplies it to the sense amplifiers, and an NMOS transistor for switching the second internal voltage from the second internal voltage supply circuit to the sense amplifiers.