Abstract: CMOS vertically modulated wells have a structure with a buried implanted layer for lateral isolation (BILLI). This structure includes a field oxide area, a first retrograde well of a first conductivity type, a second retrograde well of a second conductivity type adjacent the first well, and a BILLI layer below the first well and connected to the second well by a vertical portion. This structure has a distribution in depth underneath the field oxide which kills lateral beta while preventing damage near the surface under the field oxide.

Abstract: An electron emitting semiconductor device is provided with a P-type semiconductor layer arranged on a semiconductor substrate having an impurity concentration. A Schottky barrier electrode is arranged on a surface of the P-type semiconductor layer. Plural P.sup.+ -type area units are positioned under and facing the Schottky barrier electrode. An N.sup.+ -type area is disposed in the vicinity of the P.sup.+ -type units. The impurity concentration is such as to cause an avalanche breakdown in at least a portion of the surfaces.

Abstract: In a static random access memory (SRAM), a memory cell ratio is increased without deteriorating an integration degree of this SRAM. The static random access memory is arranged by: trenches formed in a semiconductor substrate and an insulating layer for isolating elements within a memory cell forming region; one pair of word transistors; one pair of driver transistors for constituting a flip-flop by forming channel regions of the driver transistors in side surfaces of the trenches and by cross-connecting gate electrodes thereof and drain electrodes thereof at one pair of input/output terminals of the flip-flop; and one pair of word transistors connected between the one pair of input/output terminals of the flip-flop and a bit line.

Abstract: A semiconductor device requiring fewer masking steps to manufacture. The semiconductor device includes the following layers (from bottom up): (1) a substrate; (2) a gate electrode formed on a first portion of the substrate; (3) a first semiconductor layer overlying the gate electrode and a second portion of the substrate adjacent the first portion; (4) first and second spaced doped semiconductor layers provided on a surface of the first semiconductor layer and defining an exposed portion of the first semiconductor layer; (5) first and second insulating layer respectively provided on the first and second spaced doped semiconductor layers adjacent a periphery of the exposed portion of the first semiconductor layer; (6) a first electrode overlying and in contact with the doped semiconductor layer and the first insulating layer; and (7) a second electrode overlying and in contact with the second doped semiconductor layer and the second insulating layer.

Abstract: A voltage step-down circuit includes a first transistor having an input terminal supplied with a first power supply voltage, an output terminal and a control terminal. A step-down voltage derived from the first power supply voltage is output through the output terminal when a load circuit to be driven by the voltage step-down circuit is in an active mode. The first transistor is OFF when the load circuit is in a standby mode. A first voltage dividing circuit has an input terminal connected to the output terminal of the first transistor, and an output terminal. A first control circuit controls a voltage of the control terminal of the first transistor so that, when the load circuit is in the active mode, a feedback control is performed on the basis of a result of comparing a reference voltage with a voltage of the output terminal of the first voltage dividing circuit, and so that, when the load circuit is in the standby mode, the feedback control is stopped and the first transistor is OFF.

Abstract: An bipolar transistor of BiCMOS is provided to improve the breakdown voltage between a collector and a base. A low concentration diffusion layer is provided at a main surface of a semiconductor substrate at a boundary between an outer perimeter of an external base layer and an end portion of a field oxide film. The low concentration diffusion layer expands from the main surface of the semiconductor substrate toward the inside of the substrate and has a concentration lower than the impurity concentration of the external base layer.

Abstract: An integrated circuit memory, MMIC, or other device including a dielectric comprising lead-tin zirconium-titanium oxide (PSZT). The proportion of tin ranges from 30% to 50% of the total amount of tin, zirconium and titanium. The dielectric is formed by applying a first liquid precursor having 10% excess lead to a substrate and heating it to form a first PSZT thin film, applying a second liquid precursor having 5% excess lead to the first thin film and heating to form a second thin film, then applying the first liquid precursor and heating to form a third thin film, and annealing the three thin films together to form a PSZT dielectric layer.

Abstract: An AC power controller includes at least two semiconductor regions reverse-connected in series. Each semiconductor region has an electron donor (source), an electron sink (drain) and an electron flow control electrode (gate) with characteristic curves such as those exhibited by FETs. Each semiconductor region also has an internal body diode. The gate-source voltage of a respective semiconductor region in the forward direction is set to be large enough to establish a desired limiting of the drain-source current. Yet, the gate-source voltage of the semiconductor region in the inverse mode is set to be large enough for the body diode to remain de-energized.

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom.

Abstract: Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.

Abstract: A thin film transistor includes a thin film transistor layer having a source region, a channel region and a drain region. In one implementation, a gate of the transistor is disposed laterally proximate the thin film channel region and comprises an annulus which laterally encircles the laterally proximate thin film channel region. In another implementation, a channel region of a thin film transistor extends elevationally away from a substrate. Source and drain regions are operatively associated with the channel region and are elevationally spaced therealong and apart from one another. A gate is disposed over the substrate and laterally proximate the channel region.

Abstract: In a solid state image pickup device including a semiconductor substrate, a photo/electro conversion element and a register formed within the semiconductor substrate, and an photoshield layer having a slit-type aperture for limiting light incident to the photo/electro conversion element, an optical element is provided for the slit-type aperture, to thereby pass polarized light having an electric field polarization face polarized in the longitudinal direction of the slit-type aperture.

Abstract: A semiconductor device, which acts as a resistor element, is constructed using a semiconductor substrate, a well region, a field insulation film having an element hole, a lamination layer and an impurity-doped region. The lamination layer is made by laminating a conductor layer on an insulation film, wherein the lamination layer has a closed-loop shape to cover overall periphery of an edge portion of the element hole. The impurity-doped region is formed on the well region in a self-aligned relationship with the lamination layer, wherein a P-N junction is formed between the impurity-doped region and well region with respect to the element hole and is terminated inside of the edge portion of the element hole. Another semiconductor device, which acts as a MOS transistor, is constructed using a conductor layer having a closed-loop shape, a source region and a drain region in addition to the semiconductor substrate, well region and field insulation film.

Abstract: Along the column of bonding pad (1), bidding terminal portions (2c), (3c), (4a), (5a) of bus bars (2), (3), and signal lines (4), (5) are arranged; principal wiring portions (2a), (3a) are made to extend in a 3-dimensional crossing configuration with respect to the signal lines, and they are connected to the bonding terminal portion of the bus bars, forming the IC package of the LOC type. Between the various bonding terminal portions and the various bonding pads, there exists no main wiring portion of the bus bar. Consequently, bonding wires (6), (7), (8), (9) do not straddle the bus bar principal wiring portion. As a result, when the bonding wire is not elevated, the bonding wire still does not make contact with the bus bar principal wiring portion to cause short circuit; as a result, the reliability is high and the device becomes thinner.

Abstract: A semiconductor device having an input terminal and an output terminal includes at least one high power device for supplying output current as an output section, and over-current limiting circuits, each including a over-current detection circuit, for limiting the amount of each current flowing through a plurality of bonding wires by which the output terminal is connected to an external terminal, to a current value of a desired amount or less. Thereby, an over-current condition where the current value is over an allowable current value, is avoided and blowing the bonding wire of the device can be prevented.

Abstract: A semiconductor structure having electrical conductors positioned over each other, but electrically isolated from each other, is disclosed. The lower conductor has a recess in its upper surface, and the recess is at least partially filled with an oxide-type material, thereby isolating the lower conductor from the upper conductor. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. Stacked capacitor cells incorporating this structure are also disclosed.

Abstract: A solid state photodiode is configured to have its rear face light responsive and is electrically connected to a lead frame or flexible carrier with conductor traces, which includes an aperture to allow light to impact the rear face. A photodiode with light responsive front and rear faces, with or without filters, permits various applications to be implemented relatively inexpensively when compared to prior art systems.

Abstract: A semiconductor device includes an insulating support. A strip of semiconductor material has two ends in contact with the insulating support and a midsection extending between the ends. A dielectric layer encircles the midsection, and a conductive layer encircles the dielectric layer. The conductive layer has a substantially constant width such that a gate electrode formed within the conductive layer is fully self-aligned with drain and source regions formed within the ends.

Abstract: An apparatus and a method for increasing integrated circuit density comprising semiconductor wafers, wafer portions or dice ("semiconductor elements") having conductive traces on the back side thereof. These semiconductor elements are stacked such that the traces on the back side of an upper semiconductor become part of the interconnect traces of the semiconductor stacked below. The traces lead to one or more edges of the semiconductor element such that the traces can make electrical contact with an external substrate, leadframe, or wiring arrangement.

Abstract: Electronic systems using separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly of the system. TAB technology is utilized to produce an assembly that has superior electrical characteristics because power and ground is conducted on separate low impedance conductive layers. The power and ground leads connecting the semiconductor die and external circuits are selected from the signal trace layer, cut bent downward and attached by bonding to the respective power or ground layer. A tool is disclosed for cutting the selected leads. The present invention further provides a system utilizing a wafer probe card which includes a multi-layer, relatively flexible tape-like substrate having a first conductive layer patterned to have a number of probe leads thereon.