Patents Examined by Cathy F. Lam
  • Patent number: 6843666
    Abstract: A method and apparatus for manually installing a surface mount connector having at least one ground bar on printed circuit board (PCB). The method and apparatus include inserting a ground bar along a length of a channel of an installation tool, where the channel is sized to receive the ground bar such that a portion of the ground bar extends from the channel. Both the ground bar and installation tool are disposed over a particular area of the PCB, and the tool is used to align the ground bar. The exposed portion of the ground bar is then soldered to the PCB, and the tool is used to repeat the method for the remaining unsoldered portions of the ground bar. The connector is then installed over the soldered ground bar.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: January 18, 2005
    Assignee: Tektronix, Inc.
    Inventor: Michael W. Eskridge
  • Patent number: 6840430
    Abstract: A board piece 2 of the present invention comprises a non-thermoplastic resin film 11, a thermoplastic resin film 10 formed on the non-thermoplastic resin film 11 and a metal wiring 8 formed on the surface of the thermoplastic resin film 10. Metal wiring 8 is partially exposed on board piece 2 to form a contact 12. A low-melting metal coating 13 is formed on contact 12 and two board pieces 2a, 2b are pressed against each other under heating with contacts 12a, 12b thereof being in contact with each other so that thermoplastic resin films 10a, 10b soften to adhere board pieces 2a, 2b to each other and low-melting metal coatings 13a, 13b melt and then solidify to connect contacts 12a, 12b to each other. The region of metal wiring 8 not used for connection is wiring 17 connecting contacts 12 to each other and a cover film 19 can be provided on the surface thereof. Contacts 12a, 12b can also be connected by applying ultrasonic wave.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: January 11, 2005
    Assignee: Sony Chemicals, Corp.
    Inventors: Hideyuki Kurita, Masanao Watanabe, Toshihiro Shinohara, Mitsuhiro Fukuda, Yukio Anzai
  • Patent number: 6841228
    Abstract: Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: January 11, 2005
    Assignee: International Business Machines Corporation
    Inventors: Robert Douglas Edwards, Jeffrey Alan Knight, Allen Frederick Moring, James W. Wilson
  • Patent number: 6838164
    Abstract: A method for manufacturing a printed wiring board, comprising the step of forming a hole by an energy beam such as a laser beam, wherein formation of a resin film by a substrate-material resin oozing to the inner-wall surface of a hole is prevented, by lowering the water-absorption percentage of a substrate material through the dehumidifying step as the preprocess of the hole-forming step for forming a through-hole or non-through-hole for interconnecting circuits formed on both sides or in multiple layers, thereby it is possible to realize high-quality hole-formation by preventing a defective resin film formation and obtain a high-reliability printed wiring board.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: January 4, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeru Yamane, Toshihiro Nishii, Shinji Nakamura, Masayuki Sakai
  • Patent number: 6831358
    Abstract: A heat-dissipative coating is composed of a plurality of granules having a predetermined thickness and disposed on an object, and is insulated and highly thermal-conductive. The total surface area of the granules is greater than that of the heat-dissipative coating disposed on the object, thereby rendering preferably effective heat-dissipation.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: December 14, 2004
    Assignee: Power Mate Technology Co., Ltd.
    Inventor: Aaron Tsai
  • Patent number: 6790515
    Abstract: A method of processing greensheets for use as microelectronic substrates comprises providing a greensheet having a width, a length and a thickness, bonding to the greensheet, within the greensheet width and length, a frame adapted to constrain movement of the greensheet within the frame, processing the greensheet and bonded frame, and removing the frame from the processed greensheet. The processing of the greensheet and bonded frame may include punching vias in the greensheet, filling the vias in the greensheet with conductive material, patterning the greensheet by applying conductive paste to the vias and greensheet surface, stacking the patterned greensheet and bonded frame with at least one other patterned greensheet and bonded frame, and laminating the greensheets. The frame is preferably removed from the processed greensheet after laminating the greensheets, and before the laminated greensheets are subsequently sintered.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Govindarajan Natarajan
  • Patent number: 6780494
    Abstract: A method of production of a ceramic electronic device such as a multilayer ceramic capacitor, comprising forming a first ceramic coating layer on the surface of a substrate, forming an internal electrode on the surface of the first ceramic coating layer, then forming a second ceramic coating layer on the surface of the first ceramic coating layer so as to cover the internal electrode. In this case, when a mean particle size of ceramic particles of the first ceramic coating layer is &agr;1, a thickness of the first ceramic coating layer is T1, a mean particle size of ceramic particles of the second ceramic coating layer is &agr;2, and a thickness of the second ceramic coating layer is T2, the conditions of &agr;1≦&agr;2, 0.05<&agr;1≦0.35 &mgr;m, T1<T2, and 0<T1<1.5 &mgr;m are satisfied. As a result, it is possible to provide a ceramic electronic device, in particular a multilayer ceramic capacitor, resistant to short-circuit defects, withstand voltage defects, and other structural defects.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: August 24, 2004
    Assignee: TDK Corporation
    Inventors: Ryou Kobayashi, Kaname Ueda, Yasushi Izumibe, Hitoshi Ishida, Akira Saitoh
  • Patent number: 6767616
    Abstract: A metal core substrate comprises a core layer (10) consisting of first and second metal plates (11, 12) layered with a third insulating layer (13) interposed therebetween; first and second insulating layers (20, 21) formed on the first and metal plates, respectively; first and second wiring patterns (45, 46) formed on the first and second insulating layers, respectively. A conductive layer (40) formed in a through-hole (22) penetrates the first insulating layer, the first metal plate, the third insulating layer, the second metal plate and the second insulating layer for electrically connecting the first wiring pattern with the second wiring pattern. The first metal plate (11) is electrically connected with the first wiring pattern (45) and the second wiring pattern (46), respectively, by means of a via (44) and by means a via (43).
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: July 27, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazuhiko Ooi, Masaru Yamazaki, Yukiji Watanabe, Takaaki Yazawa
  • Patent number: 6416904
    Abstract: An improved design and manufacturing method is disclosed for calendered, double side segment coated webs. By staggering the leading edges and/or the trailing edges of the segment coatings on one side of the web from those on the other side, web damage, including the incidence of breakage, can be reduced. Further, vibration and wear on the calendering apparatus can be reduced. The invention is particularly useful for heavily calendered webs such as the electrodes in non-aqueous rechargeable lithium ion batteries.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: July 9, 2002
    Assignee: E-One Moli Energy (Canada) Limited
    Inventors: Jan Naess Reimers, Akiyoshi Manabe, Alexander Man-Chung Leung
  • Patent number: 6358598
    Abstract: A flexible plastic window covering which combines the qualities of being translucent, colorful, easily installed in any size, self-adhering, removable and reusable, easily cleaned, wear and fade resistant, ultraviolet light absorbing, and decorative while providing privacy or hiding an unwanted view.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: March 19, 2002
    Inventor: Thomas Hicks
  • Patent number: 6262458
    Abstract: Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: July 17, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Hu
  • Patent number: 6238777
    Abstract: A printed-circuit board according to the present invention includes: a plurality of insulating layers; a plurality of conductive patterns formed in each insulating layer; and a plurality of closed and curved patterns each formed around the conductive patterns in each insulating layer, and each formed by a material having a coefficient of linear thermal expansion smaller than that of the insulating layer. In this case, each closed and curved pattern is made of copper and formed of same material as that of each conductive pattern. Further, when the coefficient of linear thermal expansion of each insulating layer is &agr;1, when the coefficient of linear thermal expansion of each conductive layer is &agr;2, and when the coefficient of linear thermal expansion of each closed and curved pattern is &agr;3, the following condition, i.e., &agr;1>&agr;2≧&agr;3, is satisfied.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: May 29, 2001
    Assignee: Denso Corporation
    Inventors: Ryuji Oda, Koji Kondo
  • Patent number: 6228468
    Abstract: A ceramic substrate for an integrated circuit package comprising a mixture of MgO and a glass, where the material has a coefficient of expansion greater than about 5 PPM/° C. and less than about 16 PPM/° C. In one embodiment, the material includes a low temperature composition glass which sinters in the range of about 600-1400° C., and is provided with metal traces selected from the group consisting essentially of copper, silver, gold and alloys thereof. The material preferably includes 30-80 percent MgO by weight, and the low temperature composition glass sinters in the range of about 900-1100° C. In another embodiment, the material includes a high temperature composition glass which sinters in the range of 1400-1800° C., and wherein the coefficient of expansion of the material is greater than about 8 PPM/° C. and less than about 16 PPM/° C.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: May 8, 2001
    Inventor: Nagesh K. Vodrahalli
  • Patent number: 6228466
    Abstract: A printed wiring board which has a conductor circuit (12) on an insulating substrate (10) and a surface insulating layer (14) formed on the surface of the substrate (10) including the surface of the conductor circuit (12). Part of the conductor circuit (12) has an exposed conductor section (120) having an exposed surface, and a surface insulating layer (140) around the conductor section (120) forms a recessed section at the same level of the surface of the conductor section (120) or lower than the surface. It is preferable to form a black or white solder resist layer on the surface insulating layer.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: May 8, 2001
    Assignee: Ibiden Co. Ltd.
    Inventors: Kiyotaka Tsukada, Masaru Takada, Mitsuhiro Kondo, Hiroyuki Kobayashi
  • Patent number: 6190759
    Abstract: A composition for use in making high optical contrast and UV light fluorescing dielectric material usuable in printed circuit boards, which in turn may form part of an electronic package. The composition comprises a resin, a coloring agent, and a fluorescing agent. A dielectric material is also defined that comprises a reinforcing material combined with the composition, the dielectric material forming at least one layer in combination with at least one conductive layer for the electronic package.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Gary A. Johansson, Konstantinos I. Papathomas
  • Patent number: 6187417
    Abstract: A dielectric for use in making high optical contrast and UV light fluorescing substrates usable in printed circuit boards, which in turn may form part of an electronic package. The dielectric comprises a resin, a coloring agent, and a fluorescing agent and does not include a reinforcing material. The substrate also includes a first conductive layer on the dielectric layer.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: February 13, 2001
    Assignee: International Business Machines Corporation
    Inventors: Donald S. Farquhar, Konstantinos I. Papathomas
  • Patent number: 6180221
    Abstract: An electrically conductive elastomer for grafting to thermoplastic and thermoset substrates is disclosed. If the substrate is a thermoset substrate, the electrically conductive elastomer comprises a mixture of an elastic material, a quantity of electrically conductive flakes, a thermoplastic elastomer material, and a thermoset material. If the substrate is a thermoplastic substrate, the electrically conductive elastomer comprises a mixture of an elastic material, a quantity of electrically conductive flakes, a thermoplastic elastomer material, and a thermoplastic material. The electrically conductive elastomer may further comprise a quantity of electrically conductive particles interspersed within the mixture. Alternatively, a quantity of electrically conductive particles may be imbedded in an outer surface of the electrically conductive elastomer. The electrically conductive elastomer is typically grafted to the substrate by a thermal process.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: January 30, 2001
    Assignee: Thomas & Betts International, Inc.
    Inventors: David R. Crotzer, Mark G. Hanrahan, Neill N. Silva
  • Patent number: 6171687
    Abstract: In accordance with the present invention, a low dielectric constant structural layer is produced having increased mechanical strength and having a plurality of voids that comprises a substrate layer; a low dielectric structural layer juxtaposing the substrate layer; and an infiltrating layer comprising an infiltrating material having a volatile component and a reinforcing component juxtaposing the structural layer and coating at least some of the plurality of voids. Also, methods are provided in which the mechanical strength of a structural layer having a plurality of voids is increased by a) depositing the structural layer on a substrate layer; b) providing an infiltrating material having a volatile component and a reinforcing component; c) introducing the infiltrating material into at least some of the plurality of voids; and d) treating the infiltrating material such that the structural strength is increased by a substantial amount.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: January 9, 2001
    Assignee: Honeywell International Inc.
    Inventors: Roger Leung, David Schaefer, John Sikonia
  • Patent number: 6168855
    Abstract: A polyolefin composite for a printed circuit board or antenna base material, a base material including the composite and electronic modules including the base material. The base material includes at least one dielectric layer including a polyolefin composite and at least one electroconductive layer including an electroconductive material, the dielectric and electroconductive layers being intimately bonded to one another.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: January 2, 2001
    Assignee: Polyeitan Composites Ltd.
    Inventors: Yachin Cohen, Dmitry Rein, Lev Vaykhansky
  • Patent number: RE37085
    Abstract: Bichromal balls have two hemispheres, typically one black and one white, each having different electrical properties. Each ball is enclosed within a spherical shell and then a space between the ball and shell is filled with a liquid to form a microsphere so that the ball is free to rotate in response to an electrical field. The microspheres can then be mixed into a substrate which can be formed into sheets or can be applied to any kind of surface. The result is a film which can form an image from an applied electrical field.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: March 6, 2001
    Assignee: Xerox Corporation
    Inventor: Nicholas K. Sheridon