Patents Examined by Cathy F. Lam
  • Patent number: 6066386
    Abstract: A method for making a printed circuit with a cavity is disclosed. The method comprises the step of laying a sticker sheet on a first, metallized dielectric layer and laying a second, metallized dielectric layer on the sticker sheet. The second metallized dielectric layer and the sticker sheet each have a window which is registered with the other window forming a cavity. Next, a flexible release layer is laid above the second metallized dielectric layer and a thermosetting visco-plastic material is laid on the release layer over the cavity. Next the first and second metallized dielectric layers, sticker sheet, release layer and visco-plastic material are laminated by heat and pressure to cure the sticker sheet and thereby bind the first and second metallized dielectric sheets to each other. During the lamination step, the sticker sheet flows to the perimeter of the cavity.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: May 23, 2000
    Assignee: International Business Machines Corporation
    Inventors: Christina Marie Boyko, Donald Seton Farquhar, Robert Maynard Japp, Michael Joseph Klodowski
  • Patent number: 6060169
    Abstract: A material and a method for forming a tamper-indicating identification coating are provided. The components of the coating are selected such that the coating exhibits a characteristic absorption spectrum with distinct features in individual regions during Fourier-transform infra-red (FTIR) spectroscopy. The coating components are selected to provide a distinct spectrum while, at the same time, providing a sufficiently complex spectrum such that the coating is difficult to duplicate. Also, a blowing agent in the coating decomposes to change the FTIR spectrum due to the heat associated with resoldering of an out-of-warranty electronic part marked with the identification coating to an in-warranty circuit card. In addition, the coating may contain a fluorophore to reveal the presence of a tamper-indicating identification coating, allowing a manufacturer to check the card by exposure with ultra-violet (UV) light. Further, the coating composition may be changed periodically and tracked to provide a date marker.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: May 9, 2000
    Assignee: International Business Machines Corporation
    Inventors: Joseph Paul Kuczynski, David Otto Lewis
  • Patent number: 6060150
    Abstract: A thermally conductive substrate having a structure in which inorganic filler for improving the thermal conductivity and thermosetting resin composition are included. The thermosetting resin composition has a flexibility in the not-hardened state, and becomes rigid after hardening. The thermally conductive substrate has excellent thermal radiation characteristics. The method of manufacturing the thermally conductive substrate includes: piling up (a) the thermally conductive sheets comprising 70 to 95 weight parts of an inorganic filler, and 4.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: May 9, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Hiroyuki Handa
  • Patent number: 6057036
    Abstract: A silicon dioxide layer overlies a monocrystal silicon substrate and has a first upper surface. A first monocrystal silicon layer overlies the first upper surface and has phosphorus atoms diffused. A second monocrystal silicon layer overlies the first monocrystal silicon layer. The first monocrystal silicon layer may have phosphorus or silicon atoms each of which has a positive electric charge instead of the phosphorus atoms diffused. A lattice mismatching layer may overlie the first upper surface instead of the first monocrystal silicon layer. The lattice mismatching layer has parts in each of which misfit dislocation is caused. The first and the second monocrystal silicon layers may overlie the monocrystal silicon substrate and layer, respectively. In this event, a silicon glass layer is interposed between the first and the second monocrystal silicon layers. The second monocrystal silicon layer has phosphorus atoms diffused.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: May 2, 2000
    Assignee: NEC Corporation
    Inventor: Kensuke Okonogi
  • Patent number: 6048581
    Abstract: An elastic ground plane (50) has an environmental coating (58) attached to a surface of a fabric (54) having a lo plurality of fibers. A conductive substance (56) is applied to the fabric (54) to coat the fabric (54).
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: April 11, 2000
    Assignee: McDonnell Douglas Corporation
    Inventor: John Cleveland Waldrop, III
  • Patent number: 6048623
    Abstract: The present invention comprises methods of contact printing of patterned, self-assembling monolayers of alkanethiolates, carboxylic acids, hydroxamic acids, and phosphonic acids on metallized thermoplastic films, the compositions produced thereby, and the use of these compositions. Patterned self-assembling monolayers allow for the controlled placement of fluids thereon which contain a chemically reactive, indicator functionality. The optical sensing devices produced thereby when the film is exposed to an analyte and light, can produce optical diffraction patterns which differ depending on the reaction of the self-assembling monolayer with the analyte of interest. The light can be in the visible spectrum, and be either reflected from the film, or transmitted through it, and the analyte can be any compound reacting with the fluid on the self-assembling monolayer. The present invention also provides a flexible support for a self-assembling monolayer on gold or another suitable metal.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: April 11, 2000
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventors: Dennis S. Everhart, George M. Whitesides
  • Patent number: 6046410
    Abstract: An interface includes a surface having an electrically conductive pad; a compliant coating over the surface having a via extending to the pad; metallization patterned over the compliant coating and extending into the via; a low modulus dielectric interface layer overlying the compliant coating and having an interface via extending to the metallization; and a floating pad structure including floating pad metallization patterned over the dielectric interface layer with a first portion forming a central pad and a second portion forming an extension from the central pad extending into the interface via. Another interface includes a substrate including a low modulus dielectric interface material having a hole extending at least partially therethrough and a floating contact structure including electrically conductive material coating the hole with at least some of the floating pad metallization forming an extension from the hole.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: April 4, 2000
    Assignee: General Electric Company
    Inventors: Robert John Wojnarowski, Barry Scott Whitmore, Bernard Gorowitz
  • Patent number: 6040039
    Abstract: This invention provides a silicon nitride circuit board in which a metal circuit plate is bonded to a high thermal conductive silicon nitride substrate having a thermal conductivity of not less than 60 W/m K, wherein a thickness D.sub.S of the high thermal conductive silicon nitride substrate and a thickness D.sub.M of the metal circuit plate satisfy a relational formula D.sub.S .ltoreq.2D.sub.M. The silicon nitride circuit board is characterized in that, when a load acts on the central portion of the circuit board which is held at a support interval of 50 mm, a maximum deflection is not less than 0.6 mm until the silicon nitride substrate is broken. The silicon nitride circuit board is characterized in that, when an anti-breaking test is performed to the circuit board which is held at a support interval of 50 mm, an anti-breaking strength is not less than 500 MPa.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: March 21, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Ikeda, Hiroshi Komorita, Yoshitoshi Sato, Michiyasu Komatsu, Nobuyuki Mizunoya
  • Patent number: 6040038
    Abstract: The present invention relates to a film condenser and a metalized film for manufacturing the same. The metalized film comprises a base film formed from an insulating material, and a metal coating layer formed on the base film. A plurality of uncoated portions are formed as area partition margins in the metal coating layer so as to respectively form, in the metal coating layer, a plurality of electrode regions, a plurality of fuse connecting regions surrounded by two or more of the electrode regions, and a plurality of fuse portions. The fuse portions electrically connect each one of the fuse connecting regions with the electrode regions surrounding the one of the fuse connecting regions.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: March 21, 2000
    Assignee: Mitsubishi Shindoh Co., Ltd.
    Inventor: Mitsuru Momose
  • Patent number: 6037045
    Abstract: A ceramic circuit element comprising a ceramic substrate having co-fired resistor and glass overcoat thereon in which the resistor is formed from a resistor paste consisting essentially of RuO.sub.2 powder, glass powder and a vehicle comprising an organic polymer and a solvent, the RuO.sub.2 powder and the glass powder having specific surface areas of 10 to 20 m.sup.2 /g and 4 to 14 m.sup.2 /g, respectively; the glass overcoat is formed from a glass overcoat paste consisting essentially of a glass composition and a vehicle comprising an organic polymer and a solvent, the glass composition having a specific surface area of 2 to 6 m.sup.2 /g; and the ceramic circuit substrate comprises a CaO--Al.sub.2 O.sub.3 --SiO.sub.2 --B.sub.2 O.sub.3 system or MgO--Al.sub.2 O.sub.3 --SiO.sub.2 --B.sub.2 O.sub.3 system glass and alumina.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: March 14, 2000
    Assignee: Sumitomo Metal (SMI) Electronics Devices, Inc.
    Inventor: Masashi Fukaya
  • Patent number: 6034420
    Abstract: Spacings between metal features are gap filled with HSQ without degradation of the electromigration resistance by depositing a conformal dielectric liner encapsulating the metal features before depositing the HSQ gap fill layer. Embodiments include depositing a conformal layer of a high density plasma oxide by high density plasma chemical deposition to a thickness of about 100 .ANG. to about 1,000 .ANG..
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: March 7, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Khanh Tran
  • Patent number: 6033787
    Abstract: A ceramic circuit board with a heat sink which has a long life under heat cycles. First and second aluminum plates are laminated and bonded onto both sides of a ceramic substrate through Al--Si-based brazing solders, respectively. A heat sink formed of an AlSiC-based composite material is laminated and bonded onto a surface of the first aluminum plate. The ceramic substrate is formed of AlN, Si.sub.3 N.sub.4 or Al.sub.2 O.sub.3. An Al alloy in the heat sink has an Al purity of 80-99% by weight, and the first or second aluminum plate has an Al purity not less than 99.98% by weight. The heat sink is laminated and bonded onto the first aluminum plate through the Al alloy in the heat sink.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: March 7, 2000
    Assignee: Mitsubishi Materials Corporation
    Inventors: Toshiyuki Nagase, Yoshirou Kuromitsu, Kunio Sugamura, Yoshio Kanda, Masafumi Hatsushika, Masato Otsuki
  • Patent number: 6033765
    Abstract: The present invention provides a printed circuit substrate comprising a lightweight prepreg and a conductive layer. The prepeg having uniform formation, low linear thermal expansion coefficient and good mechanical strength, comprising a porous para-oriented aromatic polyamide film and a thermoplastic resin and/or a thermosetting resin, the porous para-oriented aromatic polyamide film being impregnated with the thermoplastic resin and/or the thermosetting resin, a process for producing the same, and a printed circuit substrate/board using the same.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: March 7, 2000
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Tsutomu Takahashi, Yoshifumi Tsujimoto, Hiroaki Kumada, Hiroyuki Sato
  • Patent number: 6030706
    Abstract: A intermetal level dielectrics with copolymers of parylene and cyclic siloxances (432, 482) between metal lines plus oxides (450, 490), and vapor deposition method for the copolymerization. Fluorination of the copolymers lowers dielectric constant and increases working temperature.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: February 29, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Mona Eissa, Justin Gaynor
  • Patent number: 6030711
    Abstract: An apparatus and method for evenly applying an atomized adhesive for bonding a die to a leadframe are disclosed. In one embodiment, the apparatus includes a hood in communication with an air supply and a vacuum plenum that encompass a semiconductor device component located in a target area during adhesive application so that the adhesive is selectively applied to specific portions of the leadframe or other semiconductor device component and adhesive is not allowed outside the system. A mask or stencil may be employed for further prevention of adhesive application to undesired areas. An air purge may be employed to direct the adhesive mist toward the component to be coated. In another embodiment, a fine adhesive spray is directed against the surface of the workpiece to be coated, selected areas being masked to prevent coating. Wafers may be coated as well as leadframes.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: February 29, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Sven Evers
  • Patent number: 6030693
    Abstract: A method for producing a layer of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of selecting a core material from one of three iron/nickel alloys, namely either (i) 58% Fe/ 42% Ni; (ii) 60% Fe/39% Ni/1% Cu; or (iii) 60% Fe/38.7% Ni/.12% Mn/.07% Si; forming the core material into a panel suitable for an intended application; cleaning the panel in preparation for plating; plating the panel with copper; subjecting the plated panel to heat treatment; and circuitizing the panel as appropriate for the intended application.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: February 29, 2000
    Assignee: International Business Machines Corporation
    Inventors: Christina Marie Boyko, John Matthew Lauffer, Ronnie Charles McHatton, Issa Said Mahmoud, deceased
  • Patent number: 6027791
    Abstract: A structure for mounting a wiring board in which the wiring board including a ceramics insulating board, metallized wiring layers arranged on said insulating board, and a plurality of connection terminals mounted on said insulating board and electrically connected to said metallized wiring layer, is placed on a mother board having wiring conductors formed on the surface of an insulator which contains an organic resin, and the connection terminals of said wiring board are connected by brazing to the wiring conductors of said mother board, wherein a value F1 defined by the following formula (1):F1=L.times..DELTA..alpha./H.sup.2 (1)wherein L is a distance (mm) between the two connection terminals which are most separated away from each other among a plurality of connection terminals mounted on said insulating board, .DELTA..alpha. is a difference in the coefficient of thermal expansion (ppm/.degree. C.) between the insulating board of said wiring board and said mother board at 40 to 400.degree. C.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: February 22, 2000
    Assignee: Kyocera Corporation
    Inventors: Masahiko Higashi, Kouichi Yamaguchi, Masanari Kokubu, Hitoshi Kumatabara, Noriaki Hamada, Kenichi Nagae, Michio Shinozaki, Yasuhide Tami
  • Patent number: 6028020
    Abstract: A single crystal quartz thin film having a thickness of 5 nm to 50 .mu.m can be prepared by forming the thin film on a single crystal substrate by a sol-gel process and peeling the thin film from the substrate. The present invention can provide the single crystal quartz thin film at a low price without a large and complex apparatus.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: February 22, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Motoyuki Tanaka, Takahiro Imai, Naoji Fujimori
  • Patent number: 6025057
    Abstract: A method of fabricating an electronic package having an organic substrate. The substrate is formed of fiberglass and epoxy. In order to additively circuitize the electronic package substrate, an organic polyelectrolyte is deposited onto the organic substrate. A colloidal palladium-tin seed layer is deposited atop the organic polyelectrolyte. This is followed by depositing a photoimageable polymer atop the seed layer, and photolithographically patterning the photoimageable polymer to uncover portions of the seed. layer. The uncovered portions of the seed layer are catalytic to the electroless deposition of copper. In this way a conductive layer of copper is deposited atop the uncovered seed layer. The organic polyelectrolyte is deposited from an aqueous solution at the pH appropriate for the desired seed catalyst coating, depending on the ionizable character of the particular polyelectrolyte employed.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: February 15, 2000
    Assignee: International Business Machines Corporation
    Inventors: Anastasios Peter Angelopoulos, Gerald Walter Jones, Richard William Malek, Heike Marcello, Jeffrey McKeveny
  • Patent number: 6022616
    Abstract: This invention is an improved adhesive composition prepared from at least one organic polymer resin, an inorganic filler, and a fugitive liquid, in which the liquid and organic polymer resin are each substantially insoluble in the other; and in which the improvement comprises that the at least one organic polymer resin be present in particulate form of particle size that is 25.mu. or smaller. Adhesive compositions so prepared can be used on dies-400 mil.times.400 mil or greater on metal substrates without significant delamination.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: February 8, 2000
    Assignee: National Starch and Chemical Investment Holding Corporation
    Inventors: Bing Wu, Timothy G. Costello, Kathy M. Jun