Patents Examined by Cathy F. Lam
  • Patent number: 6906611
    Abstract: A ceramic component includes a ceramic body, electrodes applied to the ceramic body, electrical connectors that connect the electrodes with one or both of an external circuit and a voltage source, a substance that connects the electrical connectors to the electrodes, and a casing that covers the electrodes at least partly. The substance is cured and electrically conductive, and contains a precious metal that is not silver.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: June 14, 2005
    Assignee: EPCOS AG
    Inventors: Franz Schrank, Gerald Kloiber
  • Patent number: 6905726
    Abstract: The invention relates to a component having two adjacent insulating layers and to a production process therefore. The component has an activated insulating layer, which can be converted into an electrically conductive layer by metallization.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: June 14, 2005
    Assignee: Infineon Technologies AG
    Inventors: Klaus Lowack, Günter Schmid, Recai Sezi
  • Patent number: 6905757
    Abstract: An object is to provide a dielectric layer of a double-sided copper clad laminate, for use in formation of a built-in capacitor layer, which can be formed in an optional thickness without using a skeletal material and is provided with a high strength. For the purpose of achieving the object, “a dielectric filler containing resin for use in formation of the built-in capacitor layer of a printed wiring board obtained by mixing a binder resin comprising 20 to 80 parts by weight of epoxy resin (inclusive of a curing agent), 20 to 80 parts by weight of a solvent soluble aromatic polyamide resin polymer, and a curing accelerator added in an appropriate amount according to need; and a dielectric filler which is a nearly spherical dielectric powder having perovskite structure which is 0.1 to 1.0 ?m in the average particle size DIA, 0.2 to 2.0 ?m in the weight cumulative particle size D50 based on the laser diffraction scattering particle size distribution measurement method, and 4.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: June 14, 2005
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Toshifumi Matsushima, Hideaki Miwa, Akira Ichiryu, Kazuhiro Yamazaki, Tetsuro Sato, Fujio Kuwako
  • Patent number: 6906427
    Abstract: An electrical connection is formed by using a double laminated conductive fine particle provided with a conductive metal layer on the surface of a spherical elastic base particle by electroless plating and electroplating and a layer of a low-melting-point metal on the surface of the conductive metal layer and wherein the conductive metal layer comprises a plurality of metal layers.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: June 14, 2005
    Assignee: Sekisui Chemical Co., Ltd.
    Inventors: Yoshiaki Tanaka, Yoshiaki Kodera, Manabu Matsubara, Kazuhiko Kanki, Tatsuo Suzuki, Kazuo Ukai
  • Patent number: 6902824
    Abstract: This invention provides a metal foil and an etching process which overcomes the problem of etching of the copper foil layer and the plating copper layer formed on a metal clad laminate during the conventional semi-additive process for producing printed wire boards. In the present invention, the metal foil and the metal foil with carrier foil include a nickel or tin layer 0.5 to 3 ?m thick formed on the external surface of a metal clad laminate which protects the surface of the plated layer during the final flash etching of the copper foil layer.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: June 7, 2005
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Takuya Yamamoto, Takashi Kataoka, Yutaka Hirasawa, Naotomi Takahashi
  • Patent number: 6898071
    Abstract: An electrical component includes a stack of layers. The layers include dielectric layers and electrode layers. The dielectric layers have a resistance with a positive temperature coefficient. The electrode layers are electrically conductive and are interspersed among the dielectric layers. At least one of the electrode layers includes a constituent that is comprised of a base metal and that is at least partially coated with a protective layer. The protective layer includes a material that slows oxidation of the base metal.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: May 24, 2005
    Assignee: EPCOS AG
    Inventor: Lutz Kirsten
  • Patent number: 6896953
    Abstract: A wiring board including a laminate comprising: a low-temperature fired layer comprising ceramic particles ? and a glass component; and a ceramic layer comprising ceramic particles ? that do not sinter at the firing temperature of the low-temperature fired layer and a glass component, wherein the ceramic particles ? have a mean particle size larger than that of the ceramic particles ? and a specific surface area smaller than that of the ceramic particles ?.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: May 24, 2005
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Shigeru Taga, Hiroyuki Takahashi
  • Patent number: 6893709
    Abstract: A metal mask structure in which a metal mask 12 for depositing a thin layer is welded to a support frame 11 and the welding portion is placed within at least a substrate to be deposited, characterized in that a concave part 12a is formed on an opposite surface of a surface of said metal mask which is contacted to the frame, and the metal mask and the support frame are welded to each other within the concave part.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: May 17, 2005
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Eiichi Kitazume
  • Patent number: 6890629
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: May 10, 2005
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 6887560
    Abstract: A multilayer flexible wired circuit board that can provide high density wiring and also can provide reduction in thickness and size, and a producing method thereof. A four-layered flexible wired circuit board is produced by preparing a double-sided substrate in which a first conductor layer and a second conductor layer are laminated on both sides of a first insulating layer; preparing a first single-sided substrate in which a third conductor layer is laminated on one surface of a second insulating layer and a second single-sided substrate in which a fourth conductor layer is laminated on one surface of a third insulating layer; bonding the first conductor layer and the third conductor layer to each other through a first thermosetting adhesive layer; and bonding the second conductor layer and the fourth conductor layer to each other through a second thermosetting adhesive layer.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: May 3, 2005
    Assignee: Nitto Denko Corporation
    Inventors: Kei Nakamura, Satoshi Tanigawa, Hiroshi Yamazaki, Mineyoshi Hasegawa
  • Patent number: 6888239
    Abstract: The invention provides a ceramic package, a ceramic package having such a sealing structure and a fabrication method of thereof. In the ceramic package, a wall layer made of a plurality of laminated ceramic sheets and having a cavity formed in a central portion thereof is stacked on a top of a base layer made of a plurality of laminated ceramic sheets. A metal layer is coated on the wall layer around the cavity to expose an outer peripheral portion of the wall layer. A glass layer is coated on the outer peripheral portion of the wall layer, which is not coated with the metal layer, to contact with the metal layer. A lid is attached on the metal layer to seal the cavity. The glass layer is coated around the metal layer, which is attached on the ceramic wall layer around the cavity, to reinforce the bonding force between the metal layer and the underlying ceramic wall layer thereby potentially preventing creation of cracks between the metal layer and the underlying ceramic wall layer.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: May 3, 2005
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Yong Wook Kim
  • Patent number: 6876091
    Abstract: The present invention provides a wiring board in which electronic components are embedded by means of an embedding resin which attains a high mounting density of the electronic components in the wiring board, which exhibits excellent electrical properties such as insulating property, which prevents random reflection of light, and which reduces non-uniformity in color of the resin during curing thereof. The present invention includes a wiring board in which electronic components are embedded by use of an embedding resin having a dielectric constant of less than or equal to about 5 and tan ? of less than or equal to about 0.08. The embedding resin preferably contains carbon black in an amount of less than or equal to about 1.4 mass %. Moreover, the embedding resin preferably contains at least a thermosetting resin and at least one inorganic filler.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: April 5, 2005
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hiroki Takeuchi, Toshifumi Kojima, Kazushige Obayashi, Hisahito Kashima
  • Patent number: 6872468
    Abstract: In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic release material (215). The conductive metal foil layer has a an exposed surface (212) that is coated with a high temperature anti-oxidant barrier (220) and has a roughness less than 0.05 microns RMS. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the exposed surface of the conductive metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: March 29, 2005
    Assignee: Motorola, Inc.
    Inventors: Timothy B. Dean, Gregory J. Dunn, Remy J. Chelini, Claudia V. Gamboa
  • Patent number: 6872436
    Abstract: The invention provides a method for manufacturing printed wiring substrates which can manufacture printed wiring substrates each having resin dielectric layers of uniform thickness and excellent surface flatness while maintaining favorable cutting performance in a dicing step. A multi-printed wiring-substrate panel is manufactured which includes a metal plate having a first main surface and a second main surface, and resin dielectric layers disposed on the first and second main surfaces. The metal plate has first depression portions and second depression portions. The first depression portions are opened at the first main surface and arranged discontinuously along predetermined cutting lines. The second depression portions are opened at the second main surface and arranged discontinuously along the predetermined cutting lines. The multi-printed wiring-substrate panel is cut along the predetermined cutting lines into a plurality of printed wiring substrates.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: March 29, 2005
    Assignee: NGK Spark Plug Co. Ltd.
    Inventors: Tomoe Suzuki, Shinji Yuri, Kazuhisa Sato, Kozo Yamasaki
  • Patent number: 6869665
    Abstract: A wiring board includes a core layer and a pair of multilayer wiring portions. The core layer, having an upper surface and a lower surface, is formed from a resin composite which contains resin filler and encloses several pieces of carbon fiber cloth. One of the multilayer wiring portions is stacked on the upper surface of the core layer, while the other is stacked on the lower surface of the core layer. Each multilayer wiring portion is composed of a number of insulating layers and wiring patterns stacked alternately with the insulating layers. The wiring patterns of the upper and the lower wiring portions are connected to each other by conductors extending through the entire thickness of the core layer.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: March 22, 2005
    Assignee: Fujitsu Limited
    Inventors: Motoaki Tani, Nobuyuki Hayashi, Tomoyuki Abe, Yasuhito Takahashi, Yoshiyasu Saeki
  • Patent number: 6866919
    Abstract: The present invention relates to a heat-resistant film base-material-inserted B-stage resin composition sheet for producing a multilayer printed wiring board which is excellent in copper adhesive strength, heat resistance and insulating reliability particularly in the Z direction and is suitable for use, as a high density small printed wiring board, in a semiconductor-chip-mounting, small-sized and lightweight novel semiconductor plastic package, and to a use thereof.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: March 15, 2005
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Nobuyuki Ikeguchi, Morio Mori
  • Patent number: 6866892
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: March 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Patent number: 6861092
    Abstract: A process for fabricating a low loss multilayer printed circuit board using a bonding ply comprising a fluoropolymer composite substrate and a thermosetting adhesive composition is disclosed. The fluoropolymer composite comprises at least one fluoropolymer and a substrate selected from woven fabrics, nonwoven fabrics and polymeric films.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: March 1, 2005
    Assignee: Tonoga, Inc.
    Inventors: Thomas F. McCarthy, David L. Wynants, Sr.
  • Patent number: 6852427
    Abstract: The present invention is directed to an aqueous, antitarnish and adhesion promoting treatment composition, comprising: zinc ions; metal ions selected from the group consisting of tungsten ions, molybdenum ions, cobalt ions, nickel ions, zirconium ions, titanium ions, manganese ions, vanadium ions, iron ions, tin ions, indium ions, silver ions, and combinations thereof; and optionally, an electrolyte that does not contain potassium or sodium ions; wherein the treatment composition is substantially free of chromium, and wherein the treatment composition forms a coating on a substrate or material that enhances adhesion of a polymer to the material. The present invention is also directed to materials coated with the above treatment composition, and methods of coating materials using the above composition.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: February 8, 2005
    Assignee: Olin Corporation
    Inventors: Leonard R. Howell, Szuchain F. Chen
  • Patent number: 6853091
    Abstract: A printed circuit board having circuit patterns printed thereon has a plurality of composite lands each including a first land having a terminal hole formed at its center for inserting the terminal of a selected electric or electronic part or device, and a plurality of second lands each being contiguous to and extending outwards from the first land. The areas contiguous to the contours of the first and second lands have no conductive foils, such as copper foils, thereon such that the substrate surface of the printed circuit board is exposed in these areas. The exposed areas are effective to confine the thermal energy in the limited areas for soldering. And the composite land shape defines a ridged cone-like solder lump, which can fixedly grip the terminal of the part or device.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: February 8, 2005
    Assignee: Orion Electric Co., Ltd.
    Inventor: Yoshiyuki Miyajima