Abstract: A new method is provided for the creation of openings in a layer of dielectric while at the same time forming a dielectric that forms the dielectric of MIM capacitors. Under the first embodiment of the invention a layer of insulation, such as SixNy or SiON or TaN and TiN, is deposited over the surface of a semiconductor substrate, points of electrical contact have been provided in this semiconductor surface. A layer of IMD is deposited over the layer of insulation, an opening is created in the layer of IMD that aligns with and overlays a contact point over which a MIM capacitor is to be created. Under the second embodiment of the invention, a stack of three layers of a first layer of TaN followed by SiOx or SixNy followed by a second layer of TaN is used as the dielectric layer for the capacitor whereby the first layer of TaN is used as an etch stop for an opening that is etched for the creation of the upper plate of the capacitor.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen to create a clean surface region having increased nitrogen. Embodiments include treating the silicon nitride sidewall spacers with an ammonia and nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

Abstract: A non-contact post CMP clean-up process. A corrosion inhibitor is used to protect the copper (118) surface to prevent an electrochemical reaction between the p-well and n-well areas. A multi-step wet chemistry is used to clean all exposed surfaces without etching more than 100 Å of the dielectric (110), copper (118), or liner (116). The first step uses a basic solution and a surfactant (124). The second step uses a diluted HF solution (126) and the third step uses an organic acid solution (128).

Abstract: A method for forming a silicone polymer insulation film having a low dielectric constant, high thermal stability, high humidity-resistance, and high O2 plasma resistance on a semiconductor substrate is applied to a plasma CVD apparatus. The first step is introducing a silicon-containing hydrocarbon compound expressed by the general formula Si&agr;O&agr;−1(R)2&agr;−&bgr;+2(OCnH2n+1)&bgr; (&agr;, &bgr;, x, and y are integers) and then introducing the vaporized compound to the reaction chamber of the plasma CVD apparatus. The residence time of the material gas is lengthened by, for example, reducing the total flow of the reaction gas, in such a way as to form a silicone polymer film having a micropore porous structure with a low dielectric constant.

Abstract: A new method is provided that affects the polishing rate of the surface of a layer of copper, that has been deposited over the surface of a layer of dielectric. Copper damascene structures have been created in the surface of the layer of dielectric, the layer of dielectric also overlies an alignment mark. The surface of the layer of dielectric that is aligned with the alignment mark is provided with dummy damascene structures, assuring equal polishing rates for active damascene structures and the surface region of the layer of dielectric overlying an alignment mark.

Abstract: A method for determining the etch depth of a gate recess (26) in an InP based FET device (10). The source-drain, current-voltage (I-V) relationship is monitored during the etching process. As the etch depth increases, a kink is formed in the linear portion of the I-V relationship. When the kink current reaches a desired value, the etching is stopped. The kink current is a strong function of etch depth, so small differences in etch depth can be easily targeted. By controlling the etch depth, the characteristics of the transistor can be reproducibly controlled and optimized.

Abstract: The present invention intends to form bumps of desired size and shape by simple steps. For this end, pads 2 are formed on a printed circuit board 1 at the same space as pads on a semiconductor chip 5. Then, the entire upper surface of the printed circuit board 1 is covered with a resist 3 except pad formed areas. The surface of the printed circuit board 1 covered with the resist 3 is then oriented downwardly and is sprayed with molten solder from the bottom side. The molten solder attaches the pad formed surface on the printed circuit board 1 and ideal semispherical bumps 4 are formed by the influence of gravity. The printed circuit board 1 formed with the bumps 4 is aligned with the pads 6 on the semiconductor chip 5 to be transferred into a high temperature oven. The bumps 4 are molten for jointing the semiconductor chip 5 and the printed circuit board 1.

Abstract: A method of forming a side wall contact on a side wall of a contact hole in an inter-layer insulator structure by an etch-back process The method includes forming a first insulation film on a top insulation layer of the inter-layer insulator structure, forming a second insulation film to extend on the side wall and a bottom of the contact hole as well as on a surface of the first insulation film. The first insulation film has a higher etching selectivity than the top insulation layer of the inter-layer insulator structure and the second insulation film has a lower etching selectivity than the top insulation layer of the inter-layer insulator structure. The second insulation film is lower in etching selectivity than the first insulation film.

Abstract: A bipolar complementary metal oxide semiconductor device has a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by advance simulation) to provide a higher c-well implant dose while creating a narrow region with relatively low concentration in the collector depletion range to avoid low base-collector breakdown. This achieves a much lower collector series resistance to pull-up a frequency response, a collector sheet resistance which can be as low as 150 &OHgr;/sq., and fT may be increased to 20 GHz or higher.

Abstract: A semiconductor device comprises a plurality of substrates (10) disposed to be stacked one another and having interconnect patterns (12) formed on the substrates, and semiconductor chips (20) mounted on the substrates (10). The interconnect pattern (12) has a bent portion (16) projecting from a surface of the substrate (10). The bent portions (16) are stacked one another and electrically connected.

Abstract: Semiconductor wafers on a boat are inserted into a furnace chamber of a vertical oxidation/diffusion furnace, and helium gas and argon gas are injected into the furnace chamber during the insertion of the boat, so that the light helium gas fills the furnace chamber without residual air and the heavy argon gas pushes out the residual air from gaps between the semiconductor wafers.

Abstract: A method for forming ultra shallow junctions in a semiconductor wafer uses disposable spacers and a silicon cap layer to achieve ultra-low low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of a semiconductor device. Silicon nitride disposable spacers are formed over the metal layer in the region of the sidewall spacers previously formed on the sidewalls of the gate. A silicon cap layer is deposited over the metal layer and the disposable spacers. Rapid thermal annealing is performed to form the high-ohmic phase of the salicide, with the disposable spacers preventing interaction and between the cobalt and the silicon in the area between the gate and the source/drain junctions along the sidewall spacers. The silicon cap layer provides a source of silicon for consumption during the first phase of salicide formation, reducing the amount of silicon of the source/drain junctions that is consumed.

Abstract: The present invention relates to a chip scale package and a method for providing the same. The chip scale package reduces the length of interconnection through the direct contact of a semiconductor chip and output terminals without a substrate. The chip scale package includes a semiconductor chip in which electronic circuits are integrated, having several bonding pads on an upper side. Output terminals are disposed around the semiconductor chip. Bonding wires connect the bonding pads with the output terminals. The bonding wires and associated components are encapsulated by a molded material, which does not encapsulate the central base of the semiconductor chip and the output terminals.

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

Abstract: A method for forming a lightly doped drain (LDD) field effect transistor uses very thin first sidewall spacers over the gate sidewalls, in which annealing/oxidation of the sidewall spacers results in (a) the rounding of corner portions of the gate structure sidewalls adjacent the gate oxide, and (b) a very low thermal consumption comprising a small portion of the total thermal budget. Secondary sidewall spacers of greater width are then formed to act as offsets in the introduction of N-type dopants into the substrate to form source and drain contact regions. The method may be varied to accommodate various design configurations and size scaling.

Abstract: Improved methods and structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, improved methods and structures are provided for multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry encompassing a range of technologies including but not limited to the memory and logic technologies. Moreover, these improved methods and structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method for forming a semiconductor device include forming a top layer of SiO2 on a top surface of a silicon wafer. A trench layer of SiO2 is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface.

Abstract: The invention provides a pressure responsive device capable of achieving thinning or miniaturization while maintaining a high performance and a method of manufacturing a semiconductor substrate for use therein. A spacer means (6) made of polyimide is disposed on a semiconductor substrate (3) having a back plate (4), and a peripheral portion of a vibrating electrode membrane (8) is supported by the spacer (6), thereby forming a capacitor comprised of the back plate (4)/a space (9) (air)/the vibrating electrode membrane (8). Additionally, a silicon nitride membrane (7) serving as a flattening membrane is provided on the supporting surface of the spacer means (6) made of polyimide so that variation in thickness of the polyimide membrane in each apparatus is controlled. As a result, fluctuations in performance of each devices are suppressed and a highly reliable pressure responsive apparatus is obtained.

Abstract: Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectric in the peripheral region comprises a harder material, specifically silicon nitride, and has a lesser overall equivalent oxide thickness. The illustrated peripheral gate dielectric has an oxide-nitride-oxide construction. The disclosed process includes forming silicon nitride over the entire chip followed by selectively etching off the silicon nitride from the memory array region, without requiring a separate mask as compared to conventional processes. After the selective etch, oxide is grown over the entire chip, growing differentially thicker in the memory array region.

Abstract: A method, apparatus and system for controlling the amount of heat transferred to a process region (30) of a workpiece (W) from exposure with laser radiation (10) using a thermally induced reflectivity switch layer (60). The apparatus of the invention is a film stack (6) having an absorber layer (50) deposited atop the workpiece, such as a silicon wafer. A portion of the absorber layer covers the process region. The absorber layer absorbs laser radiation and converts the absorbed radiation into heat. A reflective switch layer (60) is deposited atop the absorber layer. The reflective switch layer may comprise one or more thin film layers, and preferably includes a thermal insulator layer and a transition layer. The portion of the reflective switch layer covering the process region has a temperature that corresponds to the temperature of the process region.

Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer. The TFT may be a top gate TFT wherein the thin film sublayer is formed on the semiconductor channel layer, and wherein the printed sublayer is formed over the thin film sublayer. Alternatively, the TFT may be a bottom gate TFT wherein the printed sublayer is formed over the gate electrode; wherein the thin film sublayer is formed over the printed sublayer, and wherein the semiconductor channel layer is formed on the thin film sublayer.