Abstract: According to the present invention, a semiconductor apparatus includes a semiconductor device, a case surrounding the semiconductor device, a spring terminal including a first connection portion extending to a top surface of the case, and a second connection portion provided on the top surface of the case and a control substrate provided on the second connection portion, wherein the first connection portion is connected to the semiconductor device, the second connection portion includes a first end connected to an end of the first connection portion, and a second end opposite to the first end, the second connection portion being a flat plate and having an elastic force using the first end as a supporting point, the second end contacts the control substrate with an elastic force, and the second connection portion has a constriction structure having a notch formed in a side surface along a longitudinal direction.

Abstract: A method of manufacturing elementary chips of a LED-based emissive display device, each chip including an inorganic semiconductor LED, a circuit for controlling the LED, and a plurality of areas of connection to an external device arranged on a connection surface of the chip.

Abstract: Various embodiments provide a method of detaching semiconductor material from a carrier, wherein the method comprises providing a carrier having attached thereto a layer of semiconductor material, wherein the layer comprises an edge portion; and guiding an air stream onto the edge portion of the layer of semiconductor material.

Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

Abstract: A resistive random access memory overcomes the low durability of the conventional resistive random access memory. The resistive random access memory includes a first electrode, a second electrode, an enclosing layer and an oxygen-containing resistance changing layer. The first and second electrodes are separate from each other. The enclosing layer forms a first via-hole. The oxygen-containing resistance changing layer is arranged for the first via-hole. The first and second electrodes and the enclosing layer jointly enclose the oxygen-containing resistance changing layer. Each of the first electrode, the second electrode and the enclosing layer is made of an element not containing oxygen.

Abstract: A pixel array, a display substrate and a display device are provided, the pixel array includes a plurality of pixel units, each pixel unit includes a plurality of windmill-shaped sub-pixels, each windmill-shaped sub-pixel is configured to display one primary color, each windmill-shaped sub-pixel includes a plurality of separated parts which are disposed around a center position of this windmill-shaped sub-pixel, and the plurality of separated parts are disposed apart from each other; between two adjacent separated parts of each windmill-shaped sub-pixel, a separated part of an adjacent windmill-shaped sub-pixel is disposed.

Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

Abstract: A manufacturing method of a magneto-resistive effect device, the manufacturing method includes steps of: forming an Mg film on a substrate on which a reference layer is formed and oxidizing the Mg film to form an MgO layer on the reference layer; heating the substrate on which the MgO layer is formed; after the step of heating, forming an Mg layer on the MgO layer; cooling the substrate on which the Mg layer is formed; and forming a free layer on the Mg layer in a state where the substrate is cooled by the cooling step, and the step of forming the Mg layer, the step of cooling, and the step of forming the free layer are performed in the process same process chamber.

Abstract: A method of manufacturing a semiconductor device includes: preparing a substrate processing apparatus including a substrate process chamber having a plasma-generation space where a nitrogen-containing gas is plasma-exited and a process space where a substrate is mounted in communication with the plasma-generation space, an inductive coupling structure configured by a coil and an impedance matching circuit, wherein electric field combining the coil and the circuit has a length of an integer multiple of a wavelength of an high-frequency power, and a table to mount the substrate under a lower end of the coil; mounting the substrate on the table; supplying the nitrogen-containing gas into the chamber; starting a plasma excitation of the nitrogen-containing gas by applying the high-frequency power to the coil; and nitriding a surface of the substrate with active species containing a nitrogen element at an internal pressure of the chamber ranging from 1 to 100 Pa.

Abstract: A magnetic random-access memory (MRAM) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (MTJ) structures due to external magnetic fields. A semiconductor device includes: a MRAM chip including a MRAM; and a magnetic shielding layer including an upper shielding layer and a via shielding layer. The upper shielding layer is on a top surface of the MRAM chip, and the via shielding layer extends from the upper shielding layer and passes through the MRAM chip.

Abstract: A layout of a sense amplifier includes a pre-charge and equalizer area. A pre-charge transistor, an equalizer transistor and a gate line are disposed within the pre-charge and equalizer area. The gate line and the pre-charge transistor share a share plug. The share plug serves as a gate contact plug for the gate line and a source/drain contact plug for the pre-charge transistor.

Abstract: A substrate with conductive film includes a base material; and a film of a conductive metal oxide arranged on an upper part of the base material. The film includes, by a top plan view, a first region and a second region, the second region is configured of a same material as the first region, and an electric resistance of the second region is higher than an electric resistance of the first region. The second region includes a part configured by a plurality of cellular sections surrounded by a plurality of fine cracks. In the part, each fine crack has a width of 1 nm to 50 nm, and each cellular section has a largest measure of less than 10 ?m.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a lower substrate including a display area and a non-display area surrounding the display area, wherein a plurality of pixels are formed in the display area. The OLED display also includes an embedded circuit formed in the configured to apply a plurality of signals to the pixels, and an initialization wiring formed in the non-display area and configured to apply an initialization voltage to each of the pixels. The initialization circuit is formed in a layer so as to at least partially overlap with the area of the embedded circuit.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.

Abstract: A display device is disclosed, which includes: a substrate, including a first via, a first surface and a second surface opposite to the first surface, wherein the first via has a first sidewall having a first roughness; a connecting element disposed in the first via; a bonding element disposed on the first surface, wherein the bonding element includes a third surface in contact with the connecting element, and the third surface has a second roughness; and a circuit element disposed on the second surface, wherein the circuit element electrically connects to the bonding element through the connecting element, wherein the first roughness of the first sidewall is greater than the second roughness of the third surface. In addition, a method for preparing the aforesaid display device is also disclosed.

Abstract: An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.

Abstract: A wafer processing method for processing a wafer has a front side and a back side, the front side of the wafer being formed with a plurality of crossing streets for defining a plurality of separate regions where a plurality of devices are individually formed. The wafer processing method includes the steps of first attaching a protective tape to the front side of the wafer, next heating the protective tape and the wafer, next applying a laser beam having a transmission wavelength to the wafer to the back side of the wafer along the streets, thereby forming a modified layer inside the wafer along each street, and next grinding the back side of the wafer, thereby reducing a thickness of the wafer to a predetermined thickness and also dividing the wafer into individual chips along each street where the modified layer is formed as a division start point.

Abstract: A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.

Abstract: A light-emitting element includes a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first contact electrode and a second contact electrode located on the light-emitting structure, and respectively making ohmic contact with the first conductive semiconductor layer and the second conductive semiconductor layer; an insulation layer for covering a part of the first contact electrode and the second contact electrode so as to insulate the first contact electrode and the second contact electrode; a first electrode pad and a second electrode pad electrically connected to each of the first contact electrode and the second contact electrode; and a radiation pad formed on the insulation layer, and radiating heat generated from the light-emitting structure.

Abstract: Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.