Abstract: A multi-chip package comprises a double-sided circuit board having first and second surfaces. Each surface has a package area and a peripheral area. Each package area has a chip mounting area on which a chip is attached, and a bonding area with which the chip is electrically connected. The peripheral area of the first surface has a runner area on which molding compound flows, and the peripheral area of the second surface has external connection pattern with which the bonding areas are electrically connected. In particular, the circuit board has gate holes, which are co-located on each surface to result in a common hole.

Abstract: A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor chip. Electrical connections are formed between the contacts and the semiconductor chip. An adhesive tape provided adjacent the non-active surface of the semiconductor chip and the one or more contacts positioned adjacent the semiconductor chip. An adhesive material provided between the non-active surface of the chip and the adhesive tape.

Abstract: On a piezoelectric substrate 23, there are provided surface acoustic wave devices F1 and F2 in which predetermined circuit patterns are formed, and a package substrate 11 comprising side vias 16 formed in a caved manner in the thickness direction on side surfaces on which the surface acoustic wave devices are mounted. When the side vias 16 are each assumed to have the opening width ? and the maximum depth D, a size satisfying ?/2<D is assumed. Thereby, it is possible to prevent protrusion of a soldering fillet applied on the side via.

Abstract: A semiconductor device comprises a semiconductor substrate, a conductive plug electrically connected to the semiconductor substrate, a silicon carbide film provided on the conductive plug, a metal compound film provided on the silicon carbide film and containing a metal carbide, and an electrode provided on the metal compound film.

Abstract: A BGA semiconductor device for high-speed operation and high pin counts has a base which is constituted by a core layer formed of wiring boards and surface layers provided on both sides of the core layer, and a semiconductor element mounted on the base. Through holes in a signal region of the core layer are disposed in an optimum through hole pattern in which power through holes and ground through holes are disposed adjacent to signal through holes.

Abstract: A low profile radio frequency (RF) module and package with efficient heat dissipation characteristics, and a method of assembly thereof, are provided. In some embodiments, the RF module package comprises a radio frequency integrated circuit (RFIC) attached to a recessed area of a lead frame. The RFIC has an active integrated circuit pattern and a plurality of conductors formed on input/output pads of the active integrated circuit pattern. An integrated passive device (IPD) is attached to the RFIC via the plurality of conductors. The IPD has a passive integrated circuit pattern, a plurality of electrode pads connected to nodes of the passive integrated circuit pattern, and metal-filled vias for electrically connecting the electrode pads to the plurality of conductors. The RFIC includes a plurality of heat conducting vias for conducting heat to the lead frame.

Abstract: A method of making a semiconductor device includes forming a wafer having a substrate and an interconnect structure over the substrate. The wafer also includes a plurality of die areas and a street located between a first die area of the plurality and a second die area of the plurality. A separation structure that includes metal is located in the interconnect structure. At least a portion of the separation structure is located in a saw kerf of the street. The separation structure is arranged to provide a predefined separation path for separating the first die area during a singulation process.

Abstract: In a semiconductor flip-chip package having a semiconductor die 104 as part of a substrate assembly, a lid 110 (or lid assembly) and substrate 102 are supported to prevent tilting and teetering of the lid. The lid and substrate do not adhere, so as to reduce cracking of solder joints due to thermal cycling induced by repeated system power on-off. An adhesion prohibitor 315, 325 may be applied so that a support 314, 324 does not adhere to both lid and substrate; the support 314, 324 may be prevented from adhering to both lid and substrate by a separate curing step. The arrangements and fabrication methods may be applied to many package types, including ball grid array (BGA) and land grid array (LGA) packages.

Abstract: A method for providing main power inductance to a switching power supply using bond wires of an integrated circuit packaging. A predetermined number of bond wires are connected serially between standalone die bond pads and no-connect pins of the packaging. An output of the switching power supply is connected to a first bond wire, and an output pin of the integrated circuit is connected to a last bond wire. A number of the bond wires, a length and a diameter of each bond wire, and a distance of the bond wires from a die attach paddle may be pre-selected to determined the main power inductance.

Abstract: An interconnect structure connecting two isolated metal lines in a non-display area of a TFT-array substrate. A first metal line is disposed on the substrate, covered with a first insulating layer. A second metal line is disposed on the first insulating layer and covered by a second insulating layer. ITO (indium tin oxide) wiring is disposed on the second insulating layer, electrically connecting the first and second metal lines. A passivation structure is disposed on the second insulating layer, with an opening therein to expose and surround the ITO wiring.

Abstract: A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to protrude upwardly from a surface of the interposer or other substrate. The interposer may be positioned at least partially around a slot or aperture through the substrate so as to laterally confine encapsulant material over the slot or aperture and over any intermediate conductive elements extending through the slot or aperture. The dam may be fabricated by stereolithography. A package including the interposer, the dam, and a semiconductor die to which the interposer is secured may include a sealing element between the interposer and the active surface of the die. All or part of the sealing element may also be fabricated using stereolithography. Methods and systems using machine vision in conjunction with stereolithography equipment are also disclosed.

Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Abstract: An integrated circuit comprises an integrated circuit package and a plurality of circuit elements disposed within the integrated circuit package. A plurality of wire bonds provide connections for at least one of the circuit elements. At least one wire bond in a first subset of wire bonds and at least one wire bond in a second subset of wire bonds are substantially perpendicular to one another at a crossing point of the wire bonds in a plan view of the integrated circuit.

Abstract: A package of a semiconductor device comprising an integrated circuit (10) generally comprises an inner layer (21) and an outer layer (16), which layers (16,21) have a mutual interface (24). An improved stability of the package is realized in that the interface (24) encloses a delamination area (22), which area (22) is isolated from any bond pads (18) of the integrated circuit (10). The delamination area (22) may be created by a pattern-wise activation of a surface of the inner layer (21). A quantity of a curable polymer may be disposed on this surface to achieve this.

Abstract: A bond pad structure comprising two bond pads, methods of forming the bond pad structure, an integrated circuit die incorporating the bond pad structure, and methods of using the bond pad structure are provided. Each of the bond pads comprise stacked metal layers, at least one lower metal layer and an upper metal layer. When the two pads are connected by a conductive material, they function as a single pad. The lower metal layer of one of the bond pads forms an extension that extends beneath the upper metal layer of the other of the bond pad. The lower metal extension functions to block the etching of a dielectric layer that is put down over the upper metal layers and the underlying substrate, for example, during a passivation etch to form the bond pad opening, to protect the substrate from damage.

Abstract: A MISFET in a semiconductor device has a gate insulating film provided on a substrate, a gate electrode provided on the gate insulating film, sidewalls provided on the side surfaces of the gate electrode, lightly doped diffusion layers provided in the respective regions of the substrate located below the edge portions of the gate electrodes, heavily doped diffusion layers provided in the respective regions of the substrate located laterally below the gate electrode and the sidewalls, and pocket diffusion layers covering the lower portions of the lightly doped diffusion layers and parts of the side surfaces thereof in overlapping relation with each other below the gate electrode. Impurity concentrations in the pocket diffusion layers are set such that the threshold of the MISFET has a desired value.

Abstract: A chip structure can reduce the phenomenon of overcrowding current at the conventional circular opening of the passivation layer and further causing electromigration when the current flows to the bonding pad via the transmission line. The improved structure for the side profile of the opening of the passivation layer is about a circular profile, but the portion near to the transmission line is a straight line or a curving line. When the current flows through this opening, the current density can be uniformly distributed along the straight line or the curving line, and whereby the phenomenon of overcrowding current can be reduced.

Abstract: A method of flip-chip mounting a circuit device to a substrate in a manner that avoids damage and impairment of a fragile or otherwise sensitive element on the device facing the substrate, and a circuit assembly produced thereby. The assembly includes a substrate having at least two sets of bonding sites spaced apart from each other to define an intermediate surface region therebetween. The device is attached to the bonding sites with solder connections, with the solder connections being present on a surface of the device that faces the substrate and on which the element is present so that the element overlies the intermediate surface region of the substrate. An underfill material is present between the device and the substrate and encapsulates the solder connections. The underfill material is separated from the intermediate surface region of the substrate so that the underfill material does not contact the element.

Abstract: This invention relates to a high density architecture for an integrated circuit package (10) in which a plurality of circuit communication wafers (12) are disposed in a stack with a plurality of cooling plates (14) between them, and wherein circuit communication between the communication wafers (12) is provided from wafer to wafer through the cooling plates (14). In addition, the communication wafers (12) may have integrated circuit chips (18) deposited on both sides of the wafer, and chip-to-chip communication may be provided from one surface of the wafer to another through the wafer. The resulting integrated circuit package may have any desired geometrical shape and will permit heat exchange, power and data exchange to occur in three generally mutually orthogonal directions through the package.

Abstract: Disclosed is a substrate for semiconductor package and a wire bonding method using thereof. The substrate is provided with at least one reference mark on its surface to check a loading position and a shift state of a solder mask. The reference mark is composed of a combination of a reference pattern and a solder mask opening and is positioned in any location on an outer peripheral edge of a die attachment region. The reference mark may take various shapes. A method for checking a solder mask shift using the reference mark includes comparing a design value of the reference pattern and the solder mask opening with the reference pattern and the solder mask opening, which are formed in an actual material. After the solder mask shift is calculated, a wire bonding coordinate is newly constructed in consideration of the solder mask shift. This minimizes the wire bonding error.