Abstract: The present invention is directed to a power semiconductor device in which a control circuit controls a power switching element, comprising: a semiconductor substrate having a front surface and a back surface; a capacitor disposed on the front surface side of the semiconductor substrate and being comprised of a stacked structure of a first conductive layer, an insulation film and a second conductive layer; and a bonding pad which is disposed on the front surface side to the capacitor and to which a bonding wire being connected, wherein the bonding pad are arranged overlapping the capacitor.

Abstract: A system may include a conductive plane defining a non-conductive antipad area and a second non-conductive area extending from the antipad area in at least a first direction, a dielectric plane coupled to the conductive plane, a conductive via passing through the dielectric plane and the antipad area, a conductive pad connected to an end of the conductive via, and a conductive trace coupled to the dielectric plane and connected to the conductive pad, the conductive trace extending from the conductive pad in the first direction.

Abstract: A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may be provided on the upper surface of the circuit substrate. An IC chip may be provided on the lower surface of the circuit substrate. The IC chip may have an active surface with wire lands and bump lands. Chip bumps may be provided on the bump land. The wire bonding pads of the circuit substrate may be connected to the wire lands of the IC chip using bonding wires. The chip bumps of the upper unit package may be connected to the chip bonding pads of the lower unit package. An IC chip may include a substrate. A conductive layer may be provided on the substrate. The conductive layer may define a bump land for supporting a chip bump and a wire land for connecting to a bonding wire.

Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The dies are mounted on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate. A source of each die is electrically connected to a second area of the conductive layer on the substrate. A gate of each die is electrically connected to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.

Abstract: An electrical circuit includes a multilayer printed circuit board and a housing which shields against electromagnetic interference. A portion of at least one outer layer of the printed circuit board are in the form of contact areas which are connected to a respective conductor area on a further layer of the printed circuit board. The conductor area occupies an area region that is offset with respect to the contact area and forms a bushing capacitor with a ground area of the outer layer.

Abstract: A lead frame has a plurality of first inner leads having distal end portions and parallel to each other, and a plurality of second inner leads having distal end portions opposing the distal end portions of the first inner leads, longer than the first inner leads, and parallel to each other. The semiconductor chip has a plurality of bonding pads arranged along one side of an element formation surface, and is mounted on the surfaces of the plurality of second inner leads using an insulating adhesive. The plurality of bonding wires include first bonding wires which electrically connect the distal end portions of the plurality of first inner leads to some of the plurality of bonding pads, and a plurality of second bonding wires which electrically connect the distal end portions of the plurality of second inner leads to the rest of the plurality of bonding pads.

Abstract: A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.

Abstract: A microelectronic device is made of a semiconductor substrate, a heat generating component in a layer thereof, and a body within the remaining semiconductor substrate. The body is made of materials which have a high thermal inertia and/or thermal conductivity. When high thermal conductivity materials are used, the body acts to transfer the heat away from the substrate to a heat sink.

Abstract: In some embodiments, a T-shaped heat spreader may be provided centrally within a folded stacked chip-scale package. The dice may be situated around the T-shaped heat spreader which may be made of high conductivity material. Heat may be dissipated through the T-shaped spreader 24 and downwardly through thermal vias into a printed circuit board.

Abstract: A method is disclosed to make a hard-coded bit in an integrated circuit on a semiconductor chip changeable in any one and only one metal layer of the semiconductor chip. In one embodiment, the method further comprising fabricating a cell on each metal layer of the semiconductor chip and a logic circuitry on the semiconductor chip. The cells are coupled to the inputs of the logic circuitry. The output of the logic circuitry changes in response to a change in any single cell to cause the hard-coded bit to change.

Abstract: A semiconductor device includes a semiconductor chip. A stepped member having stepped regions is provided on the semiconductor chip. The stepped member, together with a redistribution layer, is encapsulated by an encapsulating resin layer. The stepped member is exemplified by functional bumps and dummy bumps having stepped regions. The dummy bumps are electrically unconnected to the exterior, but are electrically connected to the redistribution layer.

Abstract: Method for conditioning of an electronic microcircuit designed for the production of an electronic module which can be glued by means of a simple glue or by soldering. For this purpose the microchip has a geometric shape compatible with a recess in a card provided to accommodate it and has a means serving as a mask compatible with the card. Ultimately this mask also serves to prevent an outflow of a resin coating used to protect a chip included in this type of module. The mask is glued to a support having, on a first face, the contact area, and on a second face the mask and the chip. The mask includes a window determining the placement of the chip.

Abstract: An apparatus, method, and system for electronic device packaging having stacked dice are disclosed herein. A first die has a through silicon via formed therethrough. A second die is landed on the through silicon via of the first die. A mount having a lead is coupled to the through silicon via of the first die.

Abstract: A high density memory card assembly having application for USB drive storage, flash and ROM memory cards, and similar memory card formats. A cavity is formed through a rigid laminate substrate. First and second digital memory devices (e.g., TSOP packages or bare semiconductor dies) are located within the cavity so as to be recessed relative to the top and bottom of the substrate. The recessed first and second memory devices are arranged in spaced, face-to-face alignment with one another within the cavity. The first and second memory devices are covered and protected by respective first and second memory packages that are located on the top and bottom of the substrate. By virtue of the foregoing, the memory package density of the assembly can be increased without increasing the height or area consumed by the assembly for receipt within an existing external housing.

Abstract: To provide a circuit device suitable for incorporating a semiconductor element emitting or receiving short-wavelength light. The circuit device includes a casing, a semiconductor element, and a cover portion. The casing has an opening on the top face thereof. The semiconductor element is incorporated in the casing and emits or receives light. The cover portion is made of a material transparent to the light and covers the opening. In the periphery of the opening, a concave portion is provided, and a portion of the cover portion with a certain thickness on the bottom side is accommodated in the concave portion. Since the portion of the cover portion with the certain thickness on the bottom side is accommodated in the concave portion provided in the upper portion of the casing, the position of the cover portion is accurately fixed. Accordingly, it is possible to obtain accurate relative positions of the semiconductor element accommodated within the casing and the cover portion.

Abstract: A chip or wafer comprises a semiconductor substrate, first and second transistors on the semiconductor substrate, first and second metal layers over the semiconductor substrate, an insulating layer on the first and second metal layers, a third and fourth metal layers on the insulating layer, a passivation layer over the third and fourth metal layers, and a fifth metal layer over the passivation layer. A signal is suited to be transmitted from the first transistor to the second transistor sequentially through the first, third, fifth, fourth and second metal layers.

Abstract: An optical semiconductor device includes a first set of lead frames having a first set of element mounting beds, a second set of lead frames having a second set of element mounting beds, which are arranged substantially on a same plane as the first set of element mounting beds. A light-emitting element is mounted on one of the first set of element mounting beds and having a pair of electrodes connected to the first set of lead frames respectively. A light-receiving element is arranged at a position facing to the light-emitting element and having a pair of electrodes connected to the second set of lead frames respectively. A supporting means is mounted on the second set of element mounting beds for supporting the light-receiving element at the position facing to the light-emitting element and for receiving a light emitted from the light-emitting element.

Abstract: A wiring pattern is provided on an insulating tape. Part of the wiring pattern is a connection section. An insulating resin is provided so that the connection section is coated with the insulating resin. A protrusion electrode of a semiconductor element is so positioned on the connection section so that the protrusion electrode will push away the insulating resin and be connected with the connection section. Then, the semiconductor is pressed in Direction D1. Heat is applied while pressing in Direction D1. In this way, the connection section intrudes into the protrusion electrode, thereby causing the connection section and the protrusion electrode to be connected with each other.

Abstract: On a piezoelectric substrate 23, there are provided surface acoustic wave devices F1 and F2 in which predetermined circuit patterns are formed, and a package substrate 11 comprising side vias 16 formed in a caved manner in the thickness direction on side surfaces on which the surface acoustic wave devices are mounted. When the side vias 16 are each assumed to have the opening width ? and the maximum depth D, a size satisfying ?/2<D is assumed. Thereby, it is possible to prevent protrusion of a soldering fillet applied on the side via.

Abstract: The present invention relates to a high-reliable semiconductor device in which electrodes formed on substrates are prevented from deteriorating by sealing the electrodes with a frame member rather than a sealing material. The frame member in the present invention surrounds electrodes formed on the substrates. The inside of the frame member is vacuous or filled with a gas which does not react with the electrodes such as an inert gas and, thereby, the electrodes are prevented from deteriorating by attacks of oxygen or moisture.