Abstract: In order to provide a semiconductor apparatus in which both semiconductor chips and interposers are provided on a carrier tape, electrical properties can be improved using short wiring in a wiring pattern substantially symmetric with respect to the semiconductor chips, production can become easier, and compactness and heat radiation can be improved. Semiconductor chips electrically connected to wiring formed on the carrier tape, and interposers on the carrier tape and surrounding the semiconductor chips, are provided next to each other.

Abstract: An efficient multiple-wavelength light emitting device is provided. This multiple-wavelength light emitting device comprises a light emitting layer 4 for emitting light containing wavelength components to be output, a negative electrode 5 that is positioned at the back surface of the light emitting layer and that transmits at least a portion of the light, reflecting layers 7R, 7G, and 7B, positioned at the back surface of the negative electrode, for reflecting, of the light emitted through the negative electrode to the back surface, light having specific wavelengths, which reflecting layers are stacked up in order perpendicularly to the light axis, in correspondence with the wavelengths of the light to be reflected, thus configuring a reflecting layer group 7. In the direction perpendicular to the light axis, divisions are made in any of at least two or more light emission regions which reflect light of different wavelengths.

Abstract: A semiconductor device in a computer system is described that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon at least some of which are connected to the integrated circuitry and having at least one electrically conductive wire bond made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads.

Abstract: In the case where a plurality of second semiconductor chips (2a and 2b) are bonded to the surface side of a first semiconductor chip (1) via bump electrodes (11 and 21), an interconnection (9) for directly connecting electrode terminals (22a and 22b) of the two second semiconductor chips (2a and 2b) is formed on the surface of a passivation film (17) of the first semiconductor chip (1). As a result, a semiconductor device of a COC type in which a plurality of second semiconductor chips are mounted, while obtaining generalization of the first semiconductor chip, a signal can be transmitted/received between the second semiconductor chips without changing the design of the semiconductor device in the first semiconductor chip and a method for manufacturing the semiconductor device can be provided.

Abstract: A tape carrier in accordance with the present invention is arranged so that it entirely covers one of surfaces of a semiconductor element, and has a metal pattern which is connected to a connection terminal of the semiconductor element an external device. In this arrangement, the metal pattern is exposed to the surface opposite to the surface to which the semiconductor element is connected. With this arrangement, it is possible to connect a circuit element including a semiconductor element to the wiring pattern exposed to the surface on the side opposite to the surface to which the semiconductor element is connected, of the upper and lower two surfaces that the tape carrier has. Moreover, since the metal pattern is exposed to the surface on the side opposite to the surface to which the semiconductor element is connected, a circuit element can be connected also to this surface, and a package circuit is constituted by using both of the surfaces of the tape carrier.

Abstract: Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source and drain regions is predominant, the short channel effect has a smaller effect.

Abstract: The invention relates to a semiconductor device having a substrate (1) for instance silicon, with a layer (2, 4) of at least organic material which contains a passage (6, 8) to the substrate (1). The passage (6,8) has walls (7, 9) transverse to the layer (2, 4). A metal layer (11) is applied on the substrate (1) in at least that portion which adjoins the passage (8). The organic material forming the walls (7, 9) of the passage (6, 8) is covered with an oxide liner (12), and the passage (6, 8) is filled with a metal (14). According to the invention, a metal liner (13) of Ti or Ta is provided between the oxide liner (12) and the metal (14) filling the passage (6, 8). It is achieved by this that the device has a better barrier between the organic material (2, 4) and the interconnection metal (14) and that the organic material (2, 4) has a better protection during the various steps of the process.

Abstract: Micro lead frame (MLF)-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.

Abstract: The package size of a diode is made smaller. On the element forming face of a semiconductor substrate having a p−-type conductive type, after a hyper-abrupt p+n+ junction of a p+-type diffusion layer, an n+-type hyper-abrupt layer, an n−-epitaxial layer, an n-type low resistance layer and an n+-type diffusion layer is formed, an anode electrode is formed on the top of the p+-type diffusion layer and a cathode electrode is formed on the top of the n+-type diffusion layer. Thereafter, electrode bumps are formed on the top of the anode electrode and the cathode electrode to thereby manufacture a small diode that can be facedown bonded onto a mounting board.

Abstract: A method of patterning a metal surface by electro-mechanical polishing is described. A metal surface is placed in fluid communication with an abrasive surface of a pad. The two surfaces are moved relative to each other, in acidic fluid which contains abrasive particles. An electrical circuit is formed between the metal surface and abrasive pad and a current is supplied to the circuit. The patterned surface then is processed into a useful feature such as a bottom electrode for a DRAM capacitor.

Abstract: A semiconductor device formed of a flexible or rigid substrate (10) having a gate electrode (11), a source electrode (12), and a drain electrode (13) formed thereon and organic semiconductor material (14) disposed at least partially thereover. With appropriate selection of material, the gate electrode (11) will form a Schottky junction and an ohmic contact will form between the organic semiconductor material (14) and each of the source electrode (12) and drain electrode (13). In many of the embodiments, any of the above elements can be formed through contact or non-contact printing. Sizing of the resultant device can be readily scaled to suit various needs.

Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Abstract: A buried gate region, a buried gate contact region and a gate contact region are provided on an SiC substrate. Thereby, a depletion layer expands in the channel region, and a high withstand voltage is attained in the normally off state. By applying a voltage of the built-in voltage or less to a gate, the depletion layer in the channel region becomes narrower and an ON-state resistance becomes low. Furthermore, when a voltage of the built-in voltage or more is applied to the gate, holes are injected from the gate so as to cause the conductivity modulation, and the ON-state resistance becomes further low.

Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions.

Abstract: A semiconductor wafer which is covered by an opaque resin in a dicing process includes marks formed on the semiconductor wafer, where the marks are distinguished from electrodes formed on the semiconductor wafer. In a dicing process, separating semiconductor chips from the semiconductor wafer can be precisely achieved.

Abstract: A process for fabricating a semiconductor device including the steps of: introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.

Abstract: A method of isolation of active regions on a silicon-on-insulator semiconductor device, including the steps of: providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; etching through the silicon active layer to form an isolation trench, the isolation trench defining an active region in the silicon active layer; forming a liner oxide by oxidation of exposed silicon in the isolation trench; and filling the isolation trench with a tensile stress-reducing low density trench isolation material, without thereafter densifying the tensile stress-reducing low density trench isolation material.

Abstract: A method for manufacturing a photodiode CMOS image sensor. A first well and a second well are formed in a first type substrate. An isolation layer is formed over the first well and the second well. At the same time, an isolation layer is formed over another region to pattern out an active region for forming the photodiode. A protective ring layer is formed over the peripheral area of the photodiode active region. A first gate structure and a second gate structure are formed above the first well and the second well respectively. A first type source/drain region and a second type source/drain region are formed in the first well and the second well respectively. Concurrently, a second type heavily doped layer is formed in the first type substrate inside the area enclosed by the protective ring layer. A high-energy ion implantation is carried out to form a second type lightly doped layer in the first type substrate just outside the second type heavily doped layer.

Abstract: A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer includes a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer.

Abstract: A phase change memory may have reduced reverse bias current by providing a N-channel field effect transistor coupled between a bipolar transistor and a conductive line such a row line. By coupling the gate of the MOS transistor to the row line, reverse bias current in unselected cells or in the standby mode may be reduced.