Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Abstract: Communication links, such as peripheral component interconnect express (PCIe) links between two PCIe-compatible devices, can be checked during a boot process to determine whether those links were established and trained successfully. Firmware, such as Basic Input/Output System (BIOS), can be programmed to determine links for which there are PCIe devices, and determine whether those links were established with the correct values for one or more connection parameters (e.g., speed and width). If one or more of these links was not established with the correct parameter values, the BIOS can perform up to a maximum or threshold number of retrain attempts. If those retrain attempts are unsuccessful, the BIOS can attempt up to a maximum or threshold number of reboot attempts. If, after a maximum number of reboot actions, one or more links still have not been established and trained successfully, a remedial action can be taken.

Abstract: Systems and methods for providing external bus protection for programmable logic devices (PLDs) are disclosed. An example system includes a programmable I/O bus configured to interface with a user device over an external bus interface coupled to a PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface; and a bus protection control signal generator. The bus protection control signal generator generates a default bus protection control signal for the bus protection circuit arrangement of the PLD prior to completion of a power ramp performed by the user device; an intermediate bus protection control signal for the PLD prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and an operational bus protection control signal for the PLD.

Abstract: The present technology relates to a transmission device, a reception device, a control method, a program, and a transmission and reception system capable of increasing a data transmission efficiency. In a case where a data stream is transmitted in a predetermined mode, and when a parameter that defines content of the mode is changed, the transmission device according to one aspect of the present technology switches transmission of the data stream in the mode defined by the changed parameter is started after training processing for performing data synchronization and correction of a difference between data timings of the lanes by the reception device is executed or is started without executing the training processing according to a type of a parameter to be changed. The present technology is applied to data transmission between chips.

Abstract: A data communication method is proposed which comprises: configuring a first application interface coupled operationally to a data storage management interface, for defining a correspondence between an application data message and a memory addressing zone managed by the data storage management interface; generating a data storage command on the basis of the memory addressing zone and the application data message; and issuing, by the first application interface, the data storage command message to the data storage management interface for sending the application data message to a second application interface, through the data storage management interface.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of the plurality of interface ports of the memory device, the first host system is one of a plurality of host systems. Detecting a second host system connected to a second interface port of the plurality of interface ports, the second host system is one of the plurality of host systems. Assigning a first subset of a plurality of virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV) and assigning a second subset of the plurality of VFs to the second host system using SR-IOV. Allocating a first corresponding range of logical block addresses (LBA) to each VF of the first subset of VFs and allocating a second corresponding range of LBAs to each VF of the second subset of VFs.

Abstract: A host interconnection device includes a serializing module, an analysis module, an arbitration module, a data-writing tracking module, and a data-reading tracking module. The serializing module serializes at least one first read/write request generated by at least one processing module and a second read/write request generated by a chipset module, and outputs the first read/write request or the second read/write request. The analysis module generates analysis information according to the first read/write request or the second read/write request. The arbitration module arbitrates the analysis information and snoop information, and generates arbitration information. The data-writing tracking module performs a data-writing tracking operation on the arbitration information to generate a first snoop request, a data-writing indication, and a data-writing request.

Abstract: A differential bus network comprising: a bus comprising two bus wires; at least three nodes each comprising: a transceiver comprising: bus terminals for coupling, respectively, to the two wires of the bus; a receiver arrangement configured to receive differential signalling from the bus terminals and determine a digital receive signal based on said differential signalling; and a transmitter arrangement configured to apply differential signalling to the bus terminals based on a digital transmit signal, the transmitter arrangement comprising a first transmitter configured to increase the potential difference between the wires of the bus to a first differential voltage state and maintain the first differential state and a suppression element configured to decrease the potential difference between the two wires of the bus towards a second differential voltage state, the transmitter arrangement further comprising a resistor coupled between the bus terminals configured to at least maintain the second differential v

Abstract: A data transmission system includes a host, a universal serial bus (USB) interface adaptor, a first-in first-out (FIFO) interface adaptor, a plurality of functional circuits, and a bus bridge circuit. The host accesses data according to the communications protocols of USB. The USB interface adaptor accesses data through a first port according to the communications protocols of USB, and accesses data through a second port according to the communications protocols of FIFO. The FIFO interface adaptor accesses data through a third port coupled to the second port according to the communications protocols of FIFO, and accesses data through a fourth port according to the communications protocols of a specific type of bus. The bus bridge circuit transmits the data received from the fourth port to a functional circuit according to the communications protocols of the specific type of bus.

Abstract: Generating a CAN ID represented by a predetermined bit used in CAN communication, including a first bit allocation process for allocating N-th to M-th bits of the CAN ID for use classification, a second bit allocation process for allocating O-th to P-th bits of the CAN ID for target classification, and a third bit allocation process for allocating Q-th to R-th bits of the CAN ID for data number classification (N, M, O, P, Q and R are integers and satisfy a relation of R>Q, P>O, M>N, N>P, O>R).

Abstract: The disclosure provides a USB expanding device comprising a plurality of USB type-C connection units, a transmission controller, and a main controller. Each of a USB type-C connection unit includes a USB type-C port, a multiplexer, and a power transmission controller. The USB type-C port provides for connecting to an external device. The multiplexer connects to the USB type-C port and the power transmission controller. The transmission controller connects to the multiplexers of each of the USB type-C connection units for controlling the transmission of data, and the main controller connects to the power transmission controllers of each of the USB type-C connection units to distribute power according to the charging request information of the power transmission controllers.

Abstract: To perform communication more definitely and efficiently. Communication is performed by a master that is a communication device having a communication initiative and a slave that is a communication device that performs communication under control of the master. The master assigns a group address to an arbitrary slave of a plurality of slaves joining in a bus setting a plurality of arbitrary slaves to one group and setting the group to a destination, and when it is confirmed that at least one or more slaves exit from the bus of the slaves to which the group address is assigned, the group address assigned to the remaining slaves is reset. The present technology is, for example, applicable to a bus IF.

Abstract: An electronic device is provided including a connector comprising a plurality of terminals, the connector being configured to be connected with an external device; a circuit electrically connected to at least a subset of the plurality of terminals; and a processor electrically connected to the circuit, wherein the processor is configured to detect a connection of the external device through the connector, detect a first impedance of a first electrical path including a first terminal of the plurality of terminals, detect a second impedance of a second electrical path including a second terminal of the plurality of terminals, and determine a connection direction of the external device connected through the connector, based on the first impedance and the second impedance.

Abstract: A coarse-grained reconfigurable array accelerator for solving partial differential equations for problems on a regular grid is provided. The regular grid comprises grid cells which are representative for a physical natural environment wherein a list of physical values is associated with each grid cell. The accelerator comprises configurable processing elements in an accelerator-internal grid connected by an accelerator-internal interconnect system and memory arrays comprising memory cells. The memory arrays are connected to the accelerator-internal interconnect system. Selected ones of the memory arrays are positioned within the accelerator corresponding to positions of the grid cells in the physical natural environment. Thereby, each group of the memory cells is adapted for storing the list of physical values of the corresponding grid cell of the physical natural environment.

Abstract: Embodiments of the present disclosure relate to a method, an apparatus, an electronic device and a computer readable storage medium for determining connection relationships among a plurality of chips. The method includes determining identity information of a plurality of chips managed by a host, the plurality of chips being connected by respective inter-chip communication interfaces for inter-chip communication. The method further includes allowing one or more of the plurality of chips to acquire identity information of other chips connected to the inter-chip communication interface of the one or more chips. The method further includes reading identity information of the other chips by means of a management interface of the one or more chips with regard to communicating with the host, so as to determine connection relationships among the plurality of chips.

Abstract: A memory device comprises a smart buffer, and a memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive a sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data as one of first priority sensing data and second priority sensing data, and a channel controller configured to allocate at least one channel selected from among a plurality of channels to a first channel group, allocate at least another channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sensing data in relation to the first memory area, and assign the second channel group to process the second priority sensing data in relation to the second memory area, wherein a number of data input/output (I/O) pins connected to the first channel group is greater than a number of data I/O

Abstract: A memory device provides a first memory area and a second memory area. A smart buffer includes; a priority setting unit receiving sensing data and a corresponding weight, determining a priority of the sensing data based on the corresponding weight, and classifying the sensing data as first priority sensing data or second priority sensing data based on the priority, and a channel controller allocating a channel to a first channel group, allocating another channel to a second channel group, assigning the first channel group to process the first priority sensing data in relation to the first memory area, and assigning the second channel group to process the second priority sensing data in relation to the second memory area.

Abstract: A method and electronic device for communicating audio signals with an audio input/output device is provided. The electronic device includes a USB type connection port, an audio processor configured to support conversion between a digital signal and an analog signal, and at least one processor configured to detect a connection of a peripheral device via the connection port, identify a type of the peripheral device, establish a first signal path for communicating the digital signal with the peripheral device through a first pin and/or a second pin included in the connection port based on whether the peripheral device supports a first mode, or establish a second signal path for communicating the analog signal with the peripheral device through the first pin and/or the second pin included in the connection port based on whether the peripheral device supports a second mode and whether a predetermined condition is satisfied.

Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

Abstract: Provided is a communication system including: a first communication bus available for communication of at least a first communication scheme; a second communication bus available for both communication of the first communication scheme and communication of a second communication scheme having a lower processing load than the first communication scheme; a plurality of first communication devices connected to both the first communication bus and the second communication bus; a plurality of second communication devices, connected to the second communication bus, which perform communication through the second communication scheme using the second communication bus; and a processor that detects an abnormality of the first communication bus, wherein each of the plurality of first communication devices performs communication through the first communication scheme using the first communication bus in a case where the abnormality of the first communication bus is not detected by the processor, and performs communicati