Abstract: Examples described herein provide a computer-implemented method that includes initializing a storage area network. The method further includes managing, using a virtualized fabric controller, the storage area network.

Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

Abstract: To perform communication more definitely and efficiently. In a case of transferring a communication initiative in accordance with a request by a secondary master, a master determines whether or not the secondary master that has performed the request has a group management capability. Then, when it is determined that the secondary master has no group management capability, the master instructs all communication devices connected to a bus to reset a group address, and when it is determined that the secondary master has the group management capability, the master transfers the communication initiative in a state in which the group address is set. The present technology is, for example, applicable to a bus IF.

Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

Abstract: A Universal Serial Bus (USB) Type-C and power delivery port with scalable power architecture is disclosed. In one aspect, at least two circuits for a USB port are consolidated into a single integrated circuit (IC). At least one of the at least two circuits is part of a Type-C port controller (TCPC) group of circuits including sensors associated with detecting whether a voltage and current are present at pins of a USB receptacle. At least the other one of the at least two circuits is selected from a battery-related group of circuits including a battery charging circuit, an over-voltage protection circuit, and a conditioning circuit. The more circuitry integrated into the single IC the more readily scalable the end product is for a multi-port device. Additional circuitry such as a light emitting diode (LED) driver may also be included in the single IC.

Abstract: An electronic device which schedules a plurality of tasks, and an operating method thereof. The electronic device includes a processor and a memory operatively connected to the processor, and when being executed, the memory stores instructions that cause the processor to: detect occurrence of an interrupt requesting performance of a second task while performing a first task; obtain reference values according to a time of the first task, and reference values according to a time of the second task; schedule the first task and the second task based on a reference value of the first task and a reference value of the second task which correspond to a time at which the interrupt occurs; and process the first task and the second task based on a result of the scheduling. Other embodiments are possible.

Abstract: A method of applying feedback control on peripheral units supplying energy to manufacturing units in a manufacturing facility uses a trained model, and includes: mapping supply relations between peripheral units and manufacturing units into a schema; establishing communications with sensors monitoring peripheral unit metrics indicative of energy transfer from the peripheral units to the manufacturing units; training the model based on the schema and training data gathered by communication with the sensors during a training period, the trained model predicting energy usage by the peripheral machines with a specified degree of accuracy; and during a control period following the training period, gathering further data from the sensors and minimizing energy usage by the peripheral units while supplying the total energy demanded by the manufacturing units by controlling at least one of the peripheral units based on an outcome of inputting the further data into the trained model.

Abstract: A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Abstract: Data transfer acceleration includes receiving, by a data transfer accelerator in a first node of a plurality of nodes, from a second node of the plurality of nodes, a request for data in a second state, wherein the second node stores an instance of the data in a first state; generating a message including one or more operations to transform the data from the first state to the second state; and sending the message to the second node in response to the request.

Abstract: An aspect of performing input/output (IO) flow control in a storage system includes receiving an IO latency factor for each IO of a plurality of IOs in a workload. The IO latency factor specifies a priority level. An aspect also includes receiving a component latency factor, with respect to each of the IOs in the workload, for each component of a plurality of components in the storage system. The component latency factor indicates a degree to which the component is considered in assessing the workload. An aspect also includes applying, during processing of the workload, the IO latency factor and the component latency factor to each of the corresponding IOs; and determining an effective average latency of the plurality of IOs in the workload as a function of the applied IO latency factors and the applied component latency factors.

Abstract: This disclosure provides a method that allows connector pins of a USB-C connector to be dynamically repurposed between low bandwidth USB2 traffic and high bandwidth USB3 traffic. USB-C devices can negotiate the use of these pins for a dynamic transition to another function or functions. The pins can be the four center connector pins of a USB-C connection, pins A6, A7, B6, B7, that are originally designated as USB 2.0 differential pairs Changing the function of the pins provides flexibility for communicating using USB-C connectors. For example, the disclosed method/device/system can be used to support high-resolution cameras and sensors in high-resolution virtual reality headsets via a single USB-C connection instead of a user having to connect multiple cables.

Abstract: A SoC chip includes: a bus mechanism including at least one MPU; an OTP memory configured to store bus access control information; a mode configuring module connected to at least one MPU and the OTP memory, the mode configuring module being configured to read the bus access control information from the OTP memory when the SoC chip is in a boot mode, and configure the MPU using the bus access control information, and the mode configuring module being further configured to enable the MPU and switch the SoC chip to a user mode upon configuration of the MPU. The bus access control information is stored by using the OTP memory, so that corresponding bus access control information may be written into the OTP memory according to requirements of various application scenarios, thereby being adapted to different application scenarios and having great flexibility.

Abstract: An electronic apparatus includes a semiconductor integrated circuit, another semiconductor integrated circuit connected to the semiconductor integrated circuit via a peripheral component interconnect (PCI) bus, and devices (a hard disk drive (HDD), and a dynamic random access memory (DRAM)) connected to the another semiconductor integrated circuit. The semiconductor integrated circuit transmits a predetermined instruction to the another semiconductor integrated circuit, and the another semiconductor integrated circuit shifts the PCI bus to a non-communicable state or a state communicable at low speed. Thereafter, the another semiconductor integrated circuit shifts the devices (the HDD and the DRAM) to a power saving state.

Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus and a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using a mapping table comprised by the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Abstract: A method for bus addressing includes receiving handshaking information from a component of a control system of an unmanned aerial vehicle (UAV), allocating a communication address to the component through a field bus, receiving a user instruction indicative of an index number of the component through a configuration interface, and establishing a correlation between a physical address of the component, the communication address, and the index number. The index number is configured to identify the component.

Abstract: A Controller Area Network, CAN, transceiver comprising a receiver arrangement for coupling to a CAN bus and configured to determine a differential signal from analog signalling received from the CAN bus; and a receive output for coupling to a CAN controller and wherein the receiver arrangement provides a digital output signal to the receive output based on the differential signal; wherein the receiver arrangement operates in at least a first mode in which it is configured to provide the digital output signal comprising logic 0 when the differential signal is greater than a first receiver threshold and provide the digital output signal comprising logic 1 when the differential signal is less than said first receiver threshold unless said differential signal satisfies a condition, whereupon the receiver arrangement is configured to provide the digital output signal comprising logic 0, wherein the condition comprises the differential signal being below an activity-voltage threshold.

Abstract: A data processing system includes a monitoring system, the monitoring system includes a processor and a data analysis block. The processor executes a monitoring application for monitoring an operation of a monitored system coupled to the monitoring system. When assistance is needed from the monitored system, the processor has an output coupled to the monitored system for providing an assistance request. When the assistance request is sent to the monitored system, the processor also sends a disturbance indication to the data analysis block. The disturbance indication indicates that the output data from the monitored system may be disturbed by the assistance request. The data analysis block can then take an action to reduce the effect the disturbance may have on the analysis results. A method for monitoring the monitored system is also provided.

Abstract: A docking station for receiving different types of seismic nodes, the docking station including a frame; a control module attached to the frame plural docking modules attached to the frame, wherein each docking module includes plural docking bays; a monitor attached to the frame and configured to display information about the plural docking modules; and a network connection device attached to the frame and configured to provide data transfer capabilities for each docking bay of the plural docking bays. The plural docking bays are configured to accept interchangeable ports that are compatible with the different types of seismic nodes.

Abstract: The present disclosure provides a system for monitoring I/O traffic. The system includes a memory storing information, a device, and a translation lookaside buffer (TLB). The device is configured to send a request for accessing information from the memory. The TLB includes a counter register file having counter registers, and entries having corresponding counter ID fields. The TLB is configured to receive a source identifier of the device and a virtual address associated with the request from the device, select an entry of the entries using the source identifier and the virtual address, select a counter register from the counter registers in accordance with information stored in the counter ID field of the selected entry, and update a value of the selected counter register in accordance with data transferred in association with the request.

Abstract: A method, apparatus, and system for an architecture for machine learning acceleration is presented. An apparatus includes a plurality of processing elements, each including a tightly-coupled memory, and a memory system coupled to the processing elements. A global synchronization manager is coupled to the plurality of the processing elements and to the memory system. The processing elements do not implement a coherency protocol with respect to the memory system. The processing elements implement direct memory access with respect to the memory system, and the global synchronization manager is configured to synchronize operations of the plurality of processing elements through the TCMs.