Abstract: Examples relate to operating mode configuration. An apparatus may include a memory resource storing executable instructions. Instructions may include instructions to receive a message from a host computing device coupled to the apparatus. The message may include a Host Based Media Access Control Address (HBMA). Instructions may further include instructions to configure the apparatus using the HBMA in response to a determination that the apparatus is in a particular operating mode. The apparatus may further include a processing resource to execute the instructions stored on the memory resource.

Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

Abstract: A peripheral component interconnect express (PCI-E) interface module is configured to operate as a host module or a target module. The PCI-E interface module can be employed in a system slot or one of multiple peripheral slots of a PCI-E compatible chassis. In addition, the PCI-E interface module is configured to communicate through passive copper cable or active optical cable.

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

Abstract: An Input/Output, I/O, module comprising a module body, a first connector disposed on a first part of the module body, and an I/O port disposed on a second part of the module body and electrically connected to the first connector. The I/O module is locatable in a module slot of an electronic device such that the first connector couples to a second connector of the module slot to electrically connect, the I/O port to the electronic device. A corresponding electronic device is also disclosed.

Abstract: A configurable transaction filtering and logging circuit for on-chip communications within a semiconductor chip can store filter patterns. The filter patterns can include an address range filter pattern. The circuit can monitor transactions carried by an on-chip connection fabric. The transactions can be configured to transfer data between a first core circuit and a second core circuit that are also implemented on the semiconductor chip. The circuit can execute one of a set of actions in response to detecting a transaction that matches one of the filter patterns. One of the actions can be logging the transaction to a transaction log buffer in response to detecting that the transaction matches one of the filter patterns.

Abstract: An input/output system including: an input/output base unit which has a plurality of slots into which input/output modules are pluggable; an evaluation device; and at least one cover element which is arrangeable on one of the plurality of slots of the input/output base unit. The evaluation device detects a presence of the at least one cover element at a slot of the plurality of slots.

Abstract: A universal serial includes a main body including a plurality of USB (Universal Serial Bus) terminals disposed on a circumference of an upper and a side surface of a housing, a storage portion that is buried inside an interior trim to accommodate the main body in an inner space and a cable that electrically connects a power supply and the main body, and wherein the main body is used in a state connected to the storage portion or moved to a state separated from the storage portion and connected to at least one smart device through the plurality of USB terminals.

Abstract: A graph processing optimization method that addresses the problems such as the low computation-to-communication ratio in graph environments, and high communication overhead as well as load imbalance in heterogeneous environments for graph processing. The method reduces communication overhead between accelerators by optimizing graph partitioning so as to improve system scalability.

Abstract: One aspect of the present disclosure relates to an arithmetic processor including a detection unit that detects instruction information, wherein an instruction including a processing instruction to be performed after completion of DMA (Direct Memory Access) in a DMA request instruction is described in the instruction information and a data processing unit that uses data transferred by the DMA request instruction to execute an operation corresponding to the processing instruction based on the instruction information detected by the detection unit.

Abstract: A storage device, such as a solid-state drive, is configured to receive messages, such as non-volatile memory networking messages issued by a host processor or computer, that utilize NVM Express over Fabric (NVMe-oF) or NVMe/Transmission Control Protocol communication formatting for transmitting the command over a network fabric. The storage device is configured to terminate the NVMe-oF or NVMe/TCP formatted communication at the storage drive level. The storage device may further be configured to issued reply messages that include NVMe-oF or NVMe/TCP formatting for the communication formatting used to deliver the reply messages over a network fabric.

Abstract: A file transfer method between BMCs is provided, to implement file transfer from a master BMC to a slave BMC. Firstly, a file to be transferred to the slave BMC is obtained. Then a communication connection with the slave BMC is established through an I2C bus. After the communication connection is established, the file is divided into multiple sub-files to meet transmission requirements of an IPMI. Finally, the sub-files are read, and the sub-files are sent to the slave BMC, so that the slave BMC combines the sub-files to obtain the file. A file transfer apparatus, device between BMCs and a storage medium corresponding to the method are further provided.

Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus and a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using a mapping table comprised by the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Abstract: A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.

Abstract: In a data access method, a processor of a host converts a first descriptor recognized by a virtual machine interface card of the virtual machine into a second descriptor recognized by a physical interface card of the host. The first descriptor includes a virtual machine physical memory address and a data length of accessible data. The physical interface card of the host obtains, based on the second descriptor, a physical address that is in a memory and to which the virtual machine physical memory address is mapped, and accesses the accessible data according to the physical address in the memory.

Abstract: Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.

Abstract: In some examples, an adapter includes a COMPACTFLASH EXPRESS (CFX) connector interface to connect to a CFX connector of a computer, and a device connector interface to connect to any of a plurality of different devices comprising different types of interfaces. The device connector interface includes an indicator settable to any of a plurality of different states to represent a respective type of the different types of interfaces when a device is connected to the adapter, and the CFX connector interface comprising an indicator connected to the indicator of the device connector interface.

Abstract: A data input scheduling apparatus that controls a vehicle battery and a relay for changing an electric connection between output terminals of the battery, and includes a detection unit for outputting an impact detection signal when an impact is applied to the vehicle and a control unit for outputting a relay-off signal to change the relay into an off state in response to the reception of the impact detection signal, the control unit outputting the relay-off signal according to a preset control cycle.

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Abstract: Communication links, such as peripheral component interconnect express (PCIe) links between two PCIe-compatible devices, can be checked during a boot process to determine whether those links were established and trained successfully. Firmware, such as Basic Input/Output System (BIOS), can be programmed to determine links for which there are PCIe devices, and determine whether those links were established with the correct values for one or more connection parameters (e.g., speed and width). If one or more of these links was not established with the correct parameter values, the BIOS can perform up to a maximum or threshold number of retrain attempts. If those retrain attempts are unsuccessful, the BIOS can attempt up to a maximum or threshold number of reboot attempts. If, after a maximum number of reboot actions, one or more links still have not been established and trained successfully, a remedial action can be taken.