Abstract: A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.

Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Abstract: A data processing system includes a plurality of power supply modules each having a comparing unit for comparing an output-current value supplied to a computer with a threshold value, the plurality of power supply modules continue the comparison when the output-current value is equal to or less than the threshold value and outputs an output-current excess signal to a plurality of server blades when the output-current value is equal to or greater than the threshold value, and the plurality of server blades control respectively power consumptions of the server blades to make a power consumption value of the server blades to an equal to or less than a predetermined value on a power source non-redundancy.

Abstract: In a method for controlling a data exchange between at least one set of data sinks and at least one set of data sources in circuit configurations and circuit sequences, which circuit configurations have at least one arbitration unit, the arbitration unit selects a first data sink (data sink arbitration) and a first data source (data source arbitration) according to a predefined sequence, and outputs an address of a first data source and a request signal and an address of a first data sink and a validity signal. Data of the first data source are stored in the first data sink.

Abstract: Various embodiments of the present invention are directed to a distributed lock and distributed locking protocol to allow multiple communicating entities to share access to a computing resource. Certain embodiments of the present invention employ a data storage register implemented by the communicating entities to hold a value reflective of a distributed lock state.

Abstract: A method for implementing connected input/output (I/O) hub configuration and management includes configuring a first I/O hub in wrap mode with a second I/O hub. The hubs are communicatively coupled via a wrap cable. The method further includes generating data traffic on a computing subsystem that includes the hubs. Generating traffic includes: converting, via the first hub, a request to implement a transaction into an I/O device-readable request packet and transmitting the request packet over the wrap cable; converting, via the second hub, the I/O device-readable (IODR) request packet into a system readable request and transmitting the request over a system bus; converting, via the second hub, the response to an IODR response packet, and transmitting the response packet over the wrap cable; and converting, via the first hub, the IODR response packet into a system readable response packet, and transmitting the response packet over the system bus.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. A process monitor within the bridge allows for measuring latency of commands issued on a first bus, passing through the bridge, and executed by clients coupled to the second bus. By using identification fields associated with the command, measuring the latency of each command begins with matching the identification field of the command to an integer. As the bridge passes acknowledgements back to the first bus, the monitoring of the command is stopped when an identification field associated with an acknowledgement matches the identification field of the command being monitored. Data collected include the minimum, maximum, total latency, and the number of commands monitored. From this data, the average latency can be easily calculated.

Abstract: An improved industrial automation system and communication system for implementation therein, and related methods of operation, are described herein. In at least some embodiments, the improved communication system allows communication in the form of messages between modules in different control or enterprise domains. Further, in at least some embodiments, such communications are achieved by providing a communication system including a manufacturing service bus having two internal service busses with a bridge between the internal busses. Also, in at least some embodiments, a methodology of synchronous messaging is employed.

Abstract: A super-speed USB3.0 hub is described to which, after configuration, there are more high-speed devices than super-speed devices connected. The difference in the numbers is recognized and logic is provided that responds to an upstream host that there is an equal or balanced number of super-speed and high-speed ports active. This is accomplished by providing a number of “dummy” ports that make up any actual difference. The “dummy” ports are never active and are never connected to any device.

Abstract: In one embodiment, a system comprises a memory, and a first bridge unit for processor access with the memory. The first bridge unit comprises a first arbitration unit that is coupled with an input-output bus, a memory free notification unit (“MFNU”), and the memory, and is configured to receive requests from the input-output bus and receive requests from the MFNU and choose among the requests to send to the memory on a first memory bus. The system further comprises a second bridge unit for packet data access with the memory that includes a second arbitration unit that is coupled with a packet input unit, a packet output unit, and the memory and is configured to receive requests from the packet input unit and receive requests from the packet output unit, and choose among the requests to send to the memory on a second memory bus.

Abstract: Methods and systems for conserving power using predictive models and signaling are described. Parameters of a power management policy are set based on predictions based on user activity and/or signals received from a remote computer which define a user preference. In an embodiment, the power management policy involves putting the computer into a sleep state and periodically waking it up. On waking, the computer determines whether to remain awake or to return to the sleep state dependent upon the output of a predictive model or signals that encode whether a remote user has requested that computer remain awake. Before returning to the sleep state, a wake-up timer is set and this timer triggers the computer to subsequently wake-up. The length of time that the timer is set to may depend on factors such as the request from the remote user, context sensors and usage data.

Abstract: A connector assembly includes first to fifth connectors, two PCIe slots, and an adapter board. When the first connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at the pins of the third connector are transmitted to the second group of pins of the first PCIe slot through the fourth connector, the fifth connector, and the first connector in series. When the second connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at pins of the third connector are transmitted to the fourth group of pins of the second PCIe slot through the fourth connector, the fifth connector, and the second connector in series.

Abstract: A request controller for controlling processing of requests by one or more semiconductor data processing unit. The resource controller includes a controller input for receiving a request for the processing unit to switch a context of the processing unit or to switch the processing unit from a current an operation to another operation. The resource controller includes a resource budget memory in which one or more budget value can be stored. The budget value represents an amount of a resource of the processing unit. The resource controller further has a budget controller which includes a first budget controller input connected to the request controller input. A second budget controller input is connected to the memory. A comparator is connected to the first budget controller input and the second controller input, for comparing a consumption value associated with the request with the budget value.

Abstract: The present invention relates to multimedia devices for different age groups with different ability to understand and control such multimedia devices. The invention relates more specifically to a computer device for multimedia functions, where the functions are provided in a control unit/peripheral device for the computer device. The control unit comprises all the essential functional parts and operational codes for its function and can operate alone through the display device or in combination with other peripheral devices.

Abstract: Some of the embodiments of the present disclosure provide a method for operating a first in first out (FIFO) memory system in different clock domains, the method comprising receiving a write request in a first clock domain; generating, by a write shift and truncation module in response to receiving the write request, a shifted series of binary numbers such that the shifted series of binary numbers is a reduced sub-set of a first series of binary numbers; and generating, by a binary to Gray conversion module, a series of Gray code numbers corresponding to the shifted series of binary numbers. Other embodiments are also described and claimed.

Abstract: Embodiments of the present invention are directed to a wire-free data center/server. The data center/server is wire-free in the sense that communication within a data unit of the data center/server (i.e., intra-data unit), between data units of the data center/server (inter-data unit), and between the data units and the backplane of the data center/server is performed wirelessly.

Abstract: A device for manipulating an operating state of a deterministic communication system is provided, which communication system includes a physical data bus, a plurality of nodes connected thereto, and an arrangement for transmitting messages in message frames at fixedly predefined communication cycles. The device is situated in the data bus between at least one node, from whose point of view the operating state of the communication system is manipulated, and the other nodes of the communication system. To make any desired manipulation of the operating state of the communication system possible, the manipulation device includes an arrangement for short-circuiting the data bus (2) and/or interrupting the data bus.

Abstract: Embodiments of the present invention provide an approach to provision storage resources (e.g., across an enterprise storage system (ESS) such as a general parallel file system (GPFS) or the like) for different workloads in an energy efficient manner. The system evaluates different energy profiles/workloads' energy consumption characteristics of storage devices to determine an allocation plan that reduces the energy cost (e.g., results in the lowest cost/energy consumption for handling a storage workload). In a typical embodiment, energy consumption characteristics for handling a particular storage workload will be determined. Thereafter, a type of storage device capable of handling the workload will be determined. Then, an allocation plan that results in the most efficient energy consumption for handling the workload will be developed. In general, the allocation plan is based upon the energy consumption characteristics and an energy efficiency algorithm.

Abstract: A bus arbitration system, a method of connecting a master device and a peripheral over a bus system of an IC and an IC is provided. In one embodiment, the bus arbitration system includes: (1) a bus system configured to couple master devices to peripherals, port arbiters coupled to the bus system, wherein each of the port arbiters uniquely corresponds to one of the peripherals and is configured to manage access to the uniquely corresponding peripheral and a request splitter configured to receive connection requests from the master devices for the peripherals and direct the connection requests to a specific one of the port arbiters according to a port identifier associated with each of the connection requests.

Abstract: Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed.