Patents Examined by Connie Yoha
  • Patent number: 9824737
    Abstract: A memory circuit (100), comprises a first set of memory cells (102a; 202a) configured to operate in a direct access mode or in a refresh mode and a second set of memory cells (102b; 202b) configured to operate in the direct access mode and in the refresh mode. The memory circuit (100) further comprises a controller (104) configured to receive a write request and to execute the write request for a set of memory cells being in direct access mode; and to buffer the write request for later execution for a set of memory cells being in refresh mode.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Yang Hong, Martin Ostermayr, El Mehdi Boujamaa
  • Patent number: 9824757
    Abstract: The consumption current of a TCAM device is reduced. A semiconductor device includes multiple sub-arrays each including a TCAM cell array. Each sub-array searches the corresponding part of the input search data. Each sub-array outputs the search result indicative of a match for every entry without searching, when the corresponding first control signal is activated.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: November 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Watanabe, Futoshi Igaue
  • Patent number: 9818459
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 14, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 9812181
    Abstract: A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined voltage level. The first transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the first transistor has a first threshold voltage. The second transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the second transistor having a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chou-Ying Yang, Yi-Cheng Huang, Shang-Hsuan Liu
  • Patent number: 9805807
    Abstract: A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: October 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cheon An Lee, Mu-Hui Park, Jiho Cho, Ji-Young Lee, Yoon-Hee Choi
  • Patent number: 9806082
    Abstract: According to one embodiment, a semiconductor memory device includes a sense amplifier on a semiconductor substrate, a memory cell array including a memory cell above the sense amplifier, the memory cell including a capacitor and a first transistor, the capacitor including a first electrode and a second electrode, the first transistor including a first current path and a first control electrode controlling an on/off of the first current path, the first current path including a first terminal and a second terminal, the first terminal being electrically connected to the first electrode, and a first conductive line electrically connected to the second terminal and extending along an upper surface of the semiconductor substrate in a first direction, the first conductive line being electrically connected to the sense amplifier.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: October 31, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chika Tanaka, Keiji Ikeda, Yoshihiro Ueda, Toshinori Numata, Tsutomu Tezuka
  • Patent number: 9798481
    Abstract: A memory system and operating method thereof are provided. The non-volatile memory array is configured to store data. The controller is coupled to the non-volatile memory array. The memory controller is configured to provide a special write operation to write the data in the non-volatile memory array before a board mount operation is applied, and provide a regular write operation to write the data in the non-volatile memory array after the board mount operation is applied. A read margin provided by the special write operation is larger than a read margin provided by the regular write operation.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 24, 2017
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Huei Shieh, Chuen-Der Lien, Chi-Shun Lin
  • Patent number: 9786351
    Abstract: A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: October 10, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung-Yub Lee, Geun-Il Lee, Jae-Hoon Cha
  • Patent number: 9779816
    Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
  • Patent number: 9767900
    Abstract: A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: September 19, 2017
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiangshui Miao, Yi Li, Yaxiong Zhou, Ronggang Xu, Junfeng Zhao, Zhulin Wei
  • Patent number: 9741422
    Abstract: A refresh control device may include a plurality of latch circuits configured to receive an active signal, a refresh signal, an active control signal, and a refresh control signal, and output a word line enable signal for controlling a refresh operation to banks. The refresh control device may include a command decoder configured to decode a row address in correspondence to an external command signal and generate the active signal and the refresh signal. The refresh control device may include an address buffer configured to buffer an active address and generate the active control signal. The refresh control device may include an address control circuit configured to generate the refresh control signal in correspondence to a refresh command signal.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 22, 2017
    Assignee: SK hynix Inc.
    Inventors: Min Su Park, Jae Il Kim
  • Patent number: 9734884
    Abstract: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: August 15, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Syed M. Alam, Thomas Andre
  • Patent number: 9734881
    Abstract: A memory device and a method for forming a memory device are disclosed. The memory device includes a memory cell having a storage unit coupled to a cell selector unit. The storage unit includes first and second storage elements. Each of the first and second storage elements includes first and second terminals. The second terminal of the first storage element is coupled to a write source line (SL-W) and the second terminal of the second storage element is coupled to a bit line (BL). The cell selector unit includes first and second selectors. The first selector includes a write select transistor (TW) and the second selector includes a first read transistor (TR1) and a second read transistor (TR2). The first selector is coupled to a word line (WL) for selectively coupling a write path to the storage unit and the second selector is coupled to a read line (RL) for selectively coupling a read path to the storage unit.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 15, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Vinayak Bharat Naik, Eng Huat Toh, Kiok Boone Elgin Quek
  • Patent number: 9728269
    Abstract: A semiconductor memory device includes a memory array region including normal cells and redundancy cells; a repair fuse block including a plurality of fuse sets suitable for programming repair addresses of the repair target cells as repair information, the repair fuse block being suitable for outputting the programmed repair information, in response to a boot-up signal; a fuse information storage block including a plurality of memory cells for storing the repair information outputted from the repair fuse block, the plurality of memory cells being refreshed simultaneously with the normal cells and the redundancy cells of the memory array region; and a repair control block suitable for comparing the repair information stored in the fuse information storage block and an address to generate a repair control signal to selectively activate redundant paths between the repair target cells and the redundancy cells.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: August 8, 2017
    Assignee: SK Hynik Inc.
    Inventors: Ga-Ram Park, Jun-Cheol Park
  • Patent number: 9715905
    Abstract: A computing system, processing unit, and method are disclosed for detecting a maximum voltage power supply for performing memory testing. The method includes generating, using a sense amplifier of a processing unit and based on a timing of a received pulse signal, first and second drive signals that collectively indicate which of first and second voltages is greater, the first and second voltages produced by respective first and second power supplies. The method also includes coupling, based on the first and second drive signals, the power supply corresponding to the relatively greater voltage of the first and second voltages with the memory.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, Jeffrey M. Scherer
  • Patent number: 9715926
    Abstract: A method to program a memristive device includes applying a pulse sequence including at least a series of pulses in alternating polarity to set the memristive device. The series has an odd number of pulses where odd numbered pulses have a first electrical polarity that switches the device to the state and even numbered pulse or pulses have a second electrical polarity.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: July 25, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Hans S. Cho
  • Patent number: 9697912
    Abstract: A first switch is closed to initialize a circuit by charging a capacitance of the circuit. A second switch is closed to initialize an amplifier in unity-gain configuration. The amplifier is capacitively coupled to the circuit. The first switch and the second switch are then opened to detect a leakage current of the circuit by detecting a change in an output voltage of the amplifier.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: July 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Feng Pan, Shigekazu Yamada
  • Patent number: 9697902
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory cell units, bit lines, word lines, and a controller. Each of the memory cell units includes a plurality of memory cells connected in series. Bit lines are connected respectively to the corresponding memory cell units. Each of the word lines is commonly connected to control gates of the corresponding memory cells of the memory cell units. The controller is configured to control a programming operation of data to the memory cells. The controller is configured to execute a first procedure including programming the data to the memory cell connected to the (4n?3)th (n being a natural number) bit line and the memory cell connected to the (4n?2)th bit line, and a second procedure including programming the data to the memory cell connected to the (4n?1)th bit line and the memory cell connected to the 4nth bit line.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Umezawa, Shigeru Kinoshita
  • Patent number: 9679641
    Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: June 13, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Andrea Redaelli, Fabio Pellizzer
  • Patent number: 9672893
    Abstract: A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 6, 2017
    Assignee: SK hynix Inc.
    Inventors: Chul Moon Jung, Mi Hyun Hwang, Man Keun Kang, Sang Kwon Lee