Abstract: Methods for transferring a layer of material from a source substrate having a zone of weakness onto a support substrate to fabricate a composite substrate are described. An implementation includes forming at least one recess in at least one of the source and support substrates, depositing material onto at least one of a front face of the source substrate and a front face of the support substrate, pressing the front faces of the source and support substrates together to bond the substrates, and detaching a transfer layer from the source substrate along the zone of weakness. When the front faces are pressed together, any excess material is received by the recess. The recess may advantageously include an opening in the front face of at least one of the source substrate and the support substrate.

Abstract: A color filter substrate for a liquid crystal display device includes a substrate, a plurality of black matrix regions on the substrate, a plurality of color filter layers, each disposed between adjacent ones of the plurality of black matrix regions, a panel identification at an edge of the substrate spaced apart from the plurality of black matrix regions, the panel identification and the plurality of color filter layers include a same material, an overcoat layer on the plurality of color filter layers, and a common electrode on the overcoat layer.

Abstract: A semiconductor device includes an insulating substrate, a cutout formed in side surfaces of the substrate, a conductive pad formed on the obverse surface of the substrate, an electrode formed on the reverse surface of the substrate, a semiconductor chip mounted on the substrate, and a connector which connects the pad to the electrode. The connector is arranged in the cutout.

Abstract: A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt connection, (b) generating a plasma, and (c) coupling the chuck to a high voltage connection. The three steps are carried out in any sequence. An inert gas or an inert gas and an etching gas are flowed into the chamber during the discharge sequence. Alternatively, a fluorocarbon CXFYHZ or a fluorocarbon and a gas such as O2, H2, N2, N2O, CO, CO2, He or Ar is flowed into the chamber during the discharge sequence. The method is compatible with batch or single wafer processes and is extendable to etching low k dielectric layers with poor thermal conductivity.

Abstract: A semiconductor device which is capable of suppressing short-circuit currents caused to flow through defective areas in a first semiconductor layer can be manufactured at high yield, by utilizing a method of manufacturing a semiconductor device including the steps of forming a first semiconductor layer on a substrate, forming a first transparent electroconductive layer on the first semiconductor layer, and forming a second semiconductor layer on the first transparent electroconductive layer, the method further including executing passivation treatment on defects in the first semiconductor layer before the formation of the second semiconductor layer.

Abstract: A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over the substrate. An opening can be formed at least into the insulation layer and a capacitor dielectric layer formed at least within the opening. Threshold voltage inducing material can be provided over the barrier layer but be retarded in movement into an electronic device comprised by the substrate. The dielectric layer can comprise a tantalum oxide and the barrier layer can include a silicon nitride. Providing threshold voltage shift inducing material can include oxide annealing dielectric layer such as with N2O. The barrier layer can be formed over the insulation layer, the insulation layer can be formed over the barrier layer, or the barrier layer can be formed over a first insulation layer with a second insulation layer formed over the barrier layer.

Abstract: An embodiment of the present invention includes a chuck, an imaging sensor, and a laser. The chuck holds a wafer having a front side attached to a tape. The imaging sensor obtains a scribe pattern on the front side through the tape. The laser is mounted above the chuck to mark an alignment pattern on a back side of the wafer based on the scribe pattern.

Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

Abstract: The invention relates to a method and to a device for treating semiconductor substrates. In conventional systems, the especially uncoated semiconductor substrates are fed to a treatment device through a charging sluice, said charging sluice adjoining a transfer chamber. A plurality of treatment chambers can be charged with the semiconductor substrates to be treated from said transfer chamber by first evacuating the transfer chamber and the treatment chamber and then opening the connecting door between the transfer chamber and the treatment chamber. The aim of the invention is to improve this system. To this end, at least one of the treatment chambers is operated at a low pressure or atmospheric pressure and the transfer chamber is flooded with an inert gas before the connecting door associated with the treatment chamber is opened, while a predetermined pressure difference between the transfer chamber and the treatment chamber is maintained.

Abstract: A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first dielectric layer is removed which forms a hole in the dielectric layer to expose the second conductive structure. Subsequently, the second conductive structure is removed to leave a void or tunnel in the dielectric layer where the second conductive structure had previously existed. Finally, a second dielectric layer is provided to fill the hole but to leave the void or tunnel in the dielectric layer subsequent to the formation of the second dielectric layer. An inventive structure resulting from the inventive method is also described.

Abstract: There is provided a semiconductor device comprising a Cu film provided above a main surface of a semiconductor substrate and used as a wiring, an intermediate layer formed at least on the Cu film, and an Al film formed on the intermediate layer and used as a pad, wherein the intermediate layer comprises a refractory metal nitride film and a refractory metal film formed on the refractory metal nitride film.

Abstract: A method of controlling characteristics of a compound semiconductor device, whereby the compound semiconductor device is formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of a corresponding resistivity region and the combined overlapping surface area of a corresponding pair of electrodes to the combined overlapping surface area of the corresponding pair of electrodes. In this manner, a resistivity of a resistor is precisely controlled.

Abstract: A method and an apparatus for predicting excursions based upon tool state variables. At least one semiconductor wafer is processed in a processing tool. Tool state data relating to the processing tool is acquired. The tool state data comprises at least one tool state variable. A determination is made whether an excursion of the tool health related to the processing tool has occurred based upon the tool state data. The tool state variable is modified to reduce the excursion of the tool health in response to the determination that the excursion of the tool health has occurred.

Abstract: A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages provided in a common layer. The method includes: (a) implanting an impurity of a second conductivity type in a specified region of a semiconductor layer of a first conductivity type to form a first well; (b) implanting an impurity of the second conductivity type in a specified region of the semiconductor layer to form a second well having an impurity concentration different from the first well; and (c) implanting an impurity of the first conductivity type in a specified region of the first well to form a third well.

Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.

Abstract: A sputter etch method in the semiconductor fabrication is disclosed. A sputter etch method for etching a layer on a semiconductor substrate in a chamber by RF plasma, includes loading a substrate for conditioning into the chamber, depositing a metal coating layer on the inside wall of the chamber by sputter etching the substrate for conditioning in the chamber, unloading the substrate for conditioning from the chamber, loading the semiconductor substrate with the layer, and etching the layer on the semiconductor substrate. Accordingly, the sputter etch method can enhance a reliability for a fabrication process of a semiconductor device under the environment of the substantial decrease in impurity falling probability. In other words, the impurity falling probability can be decreased by coating a metal layer on the wall of the sputter etch chamber employing a wafer on which a barrier metal layer is deposited right before a main lot in a sputter etch process.

Abstract: A method for separating a semiconductor wafer into several thousand devices or dies by laser ablation. Semiconductor wafers are initially pre-processed to create multiple devices, such as blue LEDs, on the wafers. The wafers are then mounted with tape coated with a generally high level adhesive. The mounted wafer is then placed on a vacuum chuck (which is itself positioned on a computer controlled positioning table) to hold it in place during the cutting process. The cutting surface is then covered with a protective layer to prevent contamination from the effluent resulting from the actual cutting process. A laser beam is generated and passed through optical elements and masks to create a pattern, such as a line or multiple lines. The patterned laser projection is directed at the wafer at a substantially normal angle and applied to the wafer until at least a partial cut is achieved through it.

Abstract: A method for fabricating a transistor having a fully silicided gate is described. A silicon substrate with a semi-finished transistor formed thereon is provided, wherein the transistor comprises a gate dielectric film, a silicon gate, a cap layer on the silicon gate, a spacer and a source/drain region. A raised source/drain is formed on the source/drain region, and then the cap layer is removed. Subsequently, a full silicidation process is performed to fully silicide the silicon gate.

Abstract: A first interlayer insulating film (3) having low dielectric constant is formed on an underlying insulating film (2) and a second interlayer insulating film (4) is formed on the first interlayer insulating film (3). Subsequently, a photoresist (5) having a pattern with openings above regions in which copper wirings are to be formed is formed on the second interlayer insulating film (4). Using the photoresist (5) as an etching mask, the second interlayer insulating film (4) and the first interlayer insulating film (3) are etched, to form a recess (6). Next, an ashing process using oxygen gas plasma (7) is performed, to remove the photoresist (5). This ashing process is performed under a plasma forming condition that the RF power is 300 W, the chamber pressure is 30 Pa, the oxygen flow is 100 sccm and the substrate temperature is 25° C.

Abstract: Production of an insulated-gate field-effect transistor is begun and interrupted at an uncompleted point. Then, a bipolar transistor is almost completely produced. At that point, a return is made to the production of the insulated-gate field-effect transistor. Lastly, a finishing step common to both transistors and including common thermal annealing and common siliciding is performed.