Abstract: Through holes are preformed in a ceramic sheet to form recessed portions at corners or side ends of a package 2 used for a solid-state image device. The package is positioned by allowing projections 52, 53, and 54 of a positioning jig 51 to come into contact with end faces 5 and 6 in the recessed portions along their shapes. The accuracy in combining a solid-state image element and a lens block is improved by using a method of positioning a package in which burrs caused when the package is produced by dividing a ceramic baked product do not affect the accuracy.

Abstract: An apparatus and a method for electrically testing a semiconductor wafer, the method including: (i) depositing electrical charges at certain points of a test pattern; (ii) scanning at least a portion of the test pattern such as to enhance charge differences resulting from defects; and (iii) collecting charged particles emitted from the at least scanned portion as a result of the scanning, thus providing an indication about an electrical state of the respective test structure.

Abstract: A method for forming semiconductor features, e.g., gates, line widths, thicknesses and spaces, produced by a photoresist trim procedure, in a closed loop process is presented. The methodology enables the use of optical emission spectroscopy and/or optical interferometry techniques for endpoint monitoring during resist trim etching of photoresist structures. Various types of material layers underlying photoresist structures are employed in order to provide an endpoint signal to enable closed loop control, with resultant improved targeting of photoresist mask and reproducibility. In addition, the method provides for in situ etch rate monitoring, and is not adversely affected by etch rate variances within an etching chamber during an etch process.

Abstract: In a method of manufacturing a compound semiconductor device, individual chip patterns are projected onto a (1 0 0) surface of a GaAs wafer so that the columns and rows of the chip patterns are aligned in a direction slanting by 45 degrees with respect to a [0 1 1] direction of the GaAs wafer. The wafer is diced along this slanting direction and chipping along the edges of the individual separated chips is greatly reduced.

Abstract: A method for fabricating a liquid crystal display panel is provided. A thin film transistor array is formed on a lower substrate, and a color filter array is formed on an upper substrate. The thin film transistor array has gate lines, data lines, data pads, thin film transistors and pixel electrodes. After the upper substrate and lower substrates are bonded together and cut into cells, the gate pads and the data pads at ends of the gate lines and the data lines on the lower substrate of the bonded substrates are exposed.

Abstract: A method and apparatus for assembling and packaging semiconductor dice. The semiconductor dice or assemblies of stacked and electrically interconnected semiconductor dice are placed at mutually spaced locations with respect to a common plane and encapsulated in a dielectric material so that end portions of discrete conductive elements extending outwardly from each semiconductor die adjacent the common plane are exposed through an outer surface of the dielectric material. Redistribution lines are formed to extend from the exposed end portions of the discrete conductive elements to predetermined locations over the outer surface of the encapsulant which correspond with another interconnect outline and conductive bumps formed at the predetermined locations.

Abstract: A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.

Abstract: A method for fabricating a semiconductor device, in which a sufficient misalignment margin is obtained when forming interconnections and contact holes, is provided. Dielectric layer patterns which define recesses in which damascene interconnections are to be formed, are formed. Then, first contact holes between the dielectric layer patterns are etched, and the first contact holes and the recesses are concurrently filled with a conductive material. The recesses can be filled with the conductive material by performing an etch-back process. The dielectric layer patterns are then etched, thereby forming the damascene interconnections and concurrently covering only a region in which second contact holes are to be formed with the dielectric layer patterns. Spaces between the dielectric layer patterns are filled with a mask layer, and then the dielectric layer patterns are selectively removed from the resultant structure, thereby forming the second contact holes aligned with the damascene interconnections.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device. The forming method comprises the step of forming an interlayer insulating film on a semiconductor substrate formed with a bit line. A contact plug to be in contact with the substrate is formed within the interlayer insulating film. A storage electrode is formed on the interlayer insulating film in such a manner that the storage electrode comes in contact with the contact plug. A dielectric film composed of a single composite film of Ta2O5(X)Y2O3(1?X) is also formed on the storage electrode according to ALD (Atomic Layer Deposition) technology. A diffusion barrier film is deposited on the dielectric film, and a plate electrode is formed on the diffusion barrier film. The present invention can provide a capacitor having sufficient capacitance necessary for a stable device operation by applying the Ta2O5(X)Y2O3(1?X) single composite film to the dielectric film.

Abstract: An input protection circuit is provided which has a high electrostatic discharge (ESD) breakdown voltage and can input a signal in a wide positive and negative voltage range. In a surface layer of a substrate, a well and a field insulating film are formed. An emitter region is formed in the well to form a lateral bipolar transistor having the well as its base. Another emitter region is formed in the surface layer of the substrate to form another lateral bipolar transistor having the well as its collector. A gate electrode layer is formed on the field insulating film between the well and the other emitter region to form a MOS transistor. The emitter region is connected to an input terminal, the well is connected to the gate electrode layer, and the other emitter region and substrate are connected to a ground potential.

Abstract: Nanostructure sensing devices for detecting an analyte are described. The devices include nanostructures connected to conductive elements, all on a substrate. Contact regions adjacent to points of contact between the nanostructures and the conductive elements are given special treatment. The proportion of nanostructure surface area within contact regions can be maximized to effect sensing at very low analyte concentrations. The contact regions can be passivated in an effort to prevent interaction between the environment and the contact regions for sensing at higher analyte concentrations and for reducing cross-sensing. Both contact regions and at least some portion of the nanostructures can be covered with a material that is at least partially permeable to the analyte of interest and impermeable to some other species to tune selectivity and sensitivity of the nanostructure sensing device.

Abstract: In a method to singulate a semiconductor wafer (100) into chips, trench streets (107) of predetermined depth (105a) are formed across the first, active wafer surface (102) to define the outline of the chips (101). Thereafter, the fabrication of the active first wafer surface is completed and protected. Then, the wafer is flipped to expose the second wafer surface (103), and the wafer is subjected to a cutting saw. The saw is aligned with the trenches in the first surface so that the saw cuts the second surface along streets (106), which extend the trenches through the wafer. The saw is stopped cutting at a depth (105b), when the saw streets just coalesce with the trench streets, respectively, whereby the chips are completely singulated.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming an impurity containing metal layer on the dielectric layer. A metal gate electrode is then formed from the impurity containing metal layer. Also described is a semiconductor device that comprises a metal gate electrode that is formed on a dielectric layer, which is formed on a substrate. The metal gate electrode includes a sufficient amount of an impurity to shift the workfunction of the metal gate electrode by at least about 0.1 eV.

Abstract: A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).

Abstract: A method for controlling electrical conductivity to a work piece by irradiating pulse light from a light source onto the work piece, the method comprising a step of controlling the light irradiation index S of the pulse light in a 400?S?900 range, wherein light energy, pulse width and light irradiation index are represented by E J/cm2, ? sec, and S, and the S is defined as E/?1/2.

Abstract: The present invention provides a method and associated structure for forming an electrostatically-doped carbon nanotube device. The method includes providing a carbon nanotube having a first end and a second end. The method also includes disposing a first metal contact directly adjacent to the first end of the carbon nanotube, wherein the first metal contact is electrically coupled to the first end of the carbon nanotube, and disposing a second metal contact directly adjacent to the second end of the carbon nanotube, wherein the second metal contact is electrically coupled to the second end of the carbon nanotube.

Abstract: A method for manufacturing a semiconductor device including forming a buffer film on a semiconductor substrate, forming a element partitioning trench, forming a oxidized film on the surface of the element partitioning trench, and washing the semiconductor substrate with hydrofluoric acid. The washing removes part of the buffer film, and the end of the buffer film is inwardly removed from the top edge of the element partitioning trench by a predetermined distance. The distance and the thickness of the oxidized film are represented by the expression 0?x?(d/2 sin ?), where x represents the distance, and ? represents the angle between a plane parallel to the semiconductor substrate and a side surface of the element partitioning trench.

Abstract: A semiconductor device is arranged such that a semiconductor chip having electrodes is flip chip mounted on printed substrate pads on a printed wiring substrate by a bump formed on each electrode. The semiconductor chip and the printed wiring substrate are fixed with a thermo-setting resin. A penetration hole is formed within an area where the printed substrate pad contacts each gold bump, and the gold bump has a joint section also on a side face of the penetration hole of the printed substrate pad. With this structure, the semiconductor device has a secure electrical connection between the bump and the metal pattern.

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.