Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.

Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.

Abstract: A memory test circuit apparatus and a method are provided. The method may include: compressing first test data output by a first storage array in a memory to generate first compressed data, compressing second test data output by a second storage array in the memory to generate second compressed data, compressing the first compressed data and the second compressed data to generate third compressed data, and outputting one of the first compressed data, the second compressed data and the third compressed data to determine a working condition of each of the first storage array and the second storage array. This method can provide not only a test result on a memory, but also a test result for individual storage array within the memory, which improves the efficiency of a circuit test.

Abstract: The present disclosure provides a memory device, wherein: an address latch can output a block selection control signal according to a block selection enable signal; a test mode selection unit can output a test mode selection signal according to a test mode selection instruction signal; a block selection unit outputs a block selection signal according to a mode selection signal and a block selection enable signal; when the memory enters a first test mode according to the test mode selection signal, an output buffer disables some of the input/output ports, and sequentially outputs the first input/output data and the second input/output data through un-disabled the input/output ports. The memory device according to the present disclosure can occupy less input/output ports of a test machine.

Abstract: Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.

Abstract: A self-test circuit for an integrated circuit, having a plurality of scan chains is provided, wherein each of the scan chains has a plurality of first memory elements, a data input for providing the scan chain with test data, wherein the data input is connected to one of the first memory elements, a plurality of second memory elements, and a switching apparatus having a first and a second switching position, which switching apparatus is coupled between the first memory elements and the second memory elements and is configured to respectively connect a last one of the first memory elements to a data output in the first switching position and to respectively connect the last one of the first memory elements to a first one of the second memory elements in the second switching position.

Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: There are provided a controller, an electronic system including the same, and an operating method of the controller and the memory system. The controller includes: a randomizing circuit configured to generate random data having a set number of bits; a masking circuit configured to output select random data by extracting some data according to a number of bits on which a partial encoding operation is to be performed, among the random data; an operating circuit configured to output encoded data and a portion of original data, by performing an operation sequentially on the original data and the select random data; and a cyclic redundancy check circuit configured to generate a cyclic redundancy check value by performing a cyclic redundancy check on the encoded data and the portion of original data, and output partially encoded data including the cyclic redundancy check value, the portion of original data, and the encoded data.

Abstract: The present invention relates to a self-diagnostic apparatus capable of improving safety of a device under test (DUT) by analyzing a characteristic change of a DUT, such as a semiconductor, a circuit module, or a system, in a safe operating region over time and allowing a regular test and a periodic test to be performed even while the DUT is running.

Abstract: A processing device in a memory system determines a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of write-to-read delay times for a memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of write-to-read delay times, and determines whether a ratio of the first error rate to the second error rate satisfies a threshold criterion.

Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.

Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.

Abstract: A critical data path of an integrated circuit includes a flip flop configured to receive a data input and provide a latched data output. A monitoring circuit includes a delay generator configured to receive the data input and provide a plurality of delayed data outputs corresponding to delayed versions of the data input with increasing amounts of delay, a selector circuit configured to select one of the plurality of delayed outputs based on a programmable control value, and a shadow latch coupled to an output of the selector circuit and configured to latch a value at its input to provide as a latched shadow output. A comparator circuit provides a match error indicator based on a comparison between the first latched data output and the latched shadow output, and an error indicator is provided which indicates whether or not an impending failure of the critical data path is detected.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Abstract: The semiconductor device includes a transmitting-side hierarchical block, a receiving-side hierarchical block and an inter-block circuit. The transmitting-side hierarchical block includes a first logic circuit and an output control circuit connected to the first logic circuit and controlling an output signal of the transmitting-side hierarchical block. The receiving-side hierarchical block includes a second logic circuit being scan test target and operating by receiving the output signal of the transmitting-side hierarchical block, and a test control circuit controlling the scan test of the second logic circuit. The inter-block circuit transmits the output signal of the transmitting-side hierarchical block to the receiving-side hierarchical block.

Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

Abstract: A method for execution by a computing device of a storage network for transferring data includes detecting a shutdown associated with a local flash memory of the storage network. The method further includes determining whether to transfer encoded data slices stored in the local flash memory, wherein a plurality of data segments are dispersed storage error encoded in accordance with distributed data storage parameters to produce pluralities of sets of encoded data slices that include the encoded data slices. When determining to transfer, the method includes determining a group of encoded data slices stored in the local flash memory to transfer, determining at least one storage location for storage of the group of encoded data slices, transferring the group of encoded data slices to the at least one storage location and outputting a transfer message indicating that the group of encoded data slices has been transferred.