Abstract: A storage device includes a nonvolatile memory device, a memory controller, and a buffer memory. The memory controller determines a first memory block of the nonvolatile memory device, which is targeted for a read reclaim operation, and reads target data from a target area of the first memory block. The target data are stored in the buffer memory. The memory controller reads at least a portion of the target data stored in the buffer memory in response to a read request corresponding to at least a portion of the target area.

Abstract: An integrated circuit with self-test circuit is provided.

Abstract: Embodiments of the present disclosure provide a scheme for decoding over a small subgraph which highly likely includes some errors. A controller is configured to: control the first decoder to decode the data, read from the memory device, using a parity check matrix for the error correction code; extract one or more subgraphs from the entire bipartite graph of the parity check matrix, which is defined by a plurality of variable nodes and a plurality of check nodes when a particular condition satisfied; and control the second decoder to decode the decoding result of the first decoder using a submatrix of the parity check matrix corresponding to the extracted subgraphs.

Abstract: An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time -interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and a boundary between the time interleaver groups is a boundary between Physical Layer Pipes (PLPs) of a core layer corresponding to the core layer signal.

Abstract: A circuit comprises a plurality of clock control devices. Each of the clock control devices is configured to generate a scan test clock signal for a particular clock domain in the circuit and comprises circuitry configured to select clock pulses of a fast clock signal as scan capture clock pulses for the particular clock domain based on a particular clock pulse of a slow clock signal and a scan enable signal. The order and spacing between the groups of the scan capture clock pulses for different clock domains correspond to the order and spacing of the clock pulses of the slow clock signal.

Abstract: A safety mechanism device includes measuring whether a first output signal or results meets dynamically adjustable boundary criterion. The safety mechanism compares the first output signal with at least one boundary signal that is dynamically adjusted. The safety mechanism can produce a dynamically or automatically adjusted boundary signal using a second output signal. The second output signal can mimic the first output signal.

Abstract: A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

Abstract: Devices and techniques for NAND device mixed parity management are described herein. A first portion of data that corresponds to a first data segment and a second data segment—respectively defined with respect to a structure of a NAND device—are received. A parity value using the first portion of data and the second portion of data is computed and then stored for error correction operations.

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

Abstract: A non-volatile data storage device includes memory cells arranged in a plurality of blocks and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to determine if a given block is a bad m-bit multi-level block. In an m-bit multi-level block, each memory cell is an m-bit multi-level cell (MLC), m being an integer equal to or greater than 2. Upon determining that the given block is a good m-bit multi-level block, the memory controller assigns the given block to be an m-bit multi-level user block. Upon determining that the given block is a bad m-bit multi-level block, the memory controller determines if the given block is a good n-bit block. In an n-bit block, each memory cell is an n-bit cell, n being an integer less than m. Upon determining that the given block is a good n-bit block, the memory controller assigns the given block to be an n-bit user block or an n-bit write-buffer block.

Abstract: An integrity check device includes a register array processing circuitry which generates a current cyclic redundancy check (CRC) parity value by sequentially performing a CRC calculation on a plurality of safety sensitive data, stores a reference CRC parity value, outputs a check result signal indicating whether an error occurs by activating a first path and by comparing the current CRC parity value with the reference CRC parity value when the plurality of safety sensitive data are maintained and when an operation of updating the reference CRC parity value is unnecessary, and updates the reference CRC parity value to the current CRC parity value by activating a second path when at least one of the plurality of safety sensitive data is intentionally changed and when the operation of updating the reference CRC parity value is necessary.

Abstract: An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.

Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

Abstract: A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.

Abstract: Systems, apparatus and methods are provided for loopback testing techniques for memory controllers. A memory controller that may comprise loopback testing circuitry that may comprise a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to an output of the inverter and a second input coupled to a second data output from the memory controller.

Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.

Abstract: Scan channel slicing methods and systems for testing of scan chains in an integrated circuit (IC) reduce the number of test cycles needed to effectively test all the scan chains in the IC, reducing the time and cost of testing. In scan channel slicing, rather than loading and unloading into scan chains high-power patterns having numerous switching transitions over the length of each scan chain, loading and unloading the entirety of the scan chain scan while observing it, chain load data is sliced, apportioning between the different scan chains independently observable sections (slices) of transition data in which all four bit-to-bit transitions (“0” to “0”, “0” to “1”, “1” to 0”, “1” to “1”) are ensured to exist. The remainder of the scan chain load data, which is not observed in the test procedure, can be low-transition data that consumes low dynamic power, such as mostly zeroes or mostly ones.

Abstract: A data processing system may include a memory module; and a controller configured to exchange data with the memory module in response to a request received from a host. The controller divide a first data into a first data group to error correction and a second data group not to error correction in response to the first data and a first data write request received from the host, generates a first meta data for error correction for the first data group, configures a first data chunk that includes the first data and the first meta data, and transmits the first data chunk to the memory module.

Abstract: Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a ring oscillator and a register for storage of a value indicative of an interval of time. Each instance of the measuring circuit is configured to measure passage of the interval of time based on a first clock signal, count oscillations of an output signal of the ring oscillator during the interval of time, and output a value indicating a number of oscillations counted during the interval of time.