Abstract: An object is to continuously apply voltage to a MEMS device using first to fifth or sixth transistors. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor. A gate of the first transistor is electrically connected to one of a source and a drain of the fifth transistor. A gate of the second transistor is electrically connected to the one of the source and the drain of the third transistor. A gate of the fourth transistor is electrically connected to the gate of the first transistor. The MEMS device is electrically connected to the one of the source and the drain of the first transistor.

Abstract: Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.

Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure also includes a dielectric structure over the semiconductor substrate and adjacent to the gate stack. The dielectric structure is in direct contact with the work function layer and the metal filling.

Abstract: A method for use in construction of an electronic device and a transistor structure are presented. The method comprising: providing one or more nanotubes grown on a surface of a first substrate; providing a desired electrode arrangement fabricated on a surface of a second substrate. The electrode arrangement comprises at least two elevated source and drain electrodes and one or more gate electrodes located in between said elevated source and drain electrodes. The method also comprises bringing the electrode arrangement on the second substrate to close proximity with the first substrate such that surfaces of the first and second substrates face each other; scanning said first substrate with said electrode arrangement and determining contact of electrodes of the electrode arrangement with a nanotube located on the first substrate; and detaching said nanotube from the first substrate to provide a transistor structure comprising an isolated nanotube between the source and drain electrodes.

Abstract: A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.

Abstract: A method forms first and second sets of fins. The first set includes a first stack of layer pairs where each layer pair contains a layer of Si having a first thickness and a layer of SiGe having a second thickness. The second set of fins includes a second stack of layer pairs where at least one layer pair contains a layer of Si having the first thickness and a layer of SiGe having a third thickness greater than the second thickness. The method further includes removing the layers of SiGe from the first stack leaving first stacked Si nanowires spaced apart by a first distance and from the second stack leaving second stacked Si nanowires spaced apart by a second distance corresponding to the third thickness. The method further includes forming a first dielectric layer on the first nanowires and a second, thicker dielectric layer on the second nanowires.

Abstract: The present disclosure provides a semiconductor structure, comprising a substrate, dielectric layers and conductive layers. A first dielectric layer is disposed on a bottom surface and sidewall surfaces of a filled trench of the substrate. A first conductive layer is disposed on the first dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A second dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the second dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A third dielectric layer is disposed on the second conductive layer. A third conductive layer is disposed in the filled trench and on the third dielectric layer. A top surface of the third conductive layer is lower than the second surface of the second conductive layer.

Abstract: A first light-emitting element and a second light-emitting element that have a resonance structure that causes output light from a light-emission functional layer to resonate between a reflective layer and a semi-transmissive reflective layer, and a pixel definition layer, and in which an aperture part is formed to correspond to each of the first light-emitting element and the second light-emitting element, are formed on a base. A first interval between the reflective layer and the semi-transmissive reflective layer in the first light-emitting element and a second interval between the reflective layer and the semi-transmissive reflective layer in the second light-emitting element are different, and a film thickness of the pixel definition layer is less than a difference between the first interval and the second interval.

Abstract: A method forms first and second sets of fins. The first set includes a first stack of layer pairs where each layer pair contains a layer of Si having a first thickness and a layer of SiGe having a second thickness. The second set of fins includes a second stack of layer pairs where at least one layer pair contains a layer of Si having the first thickness and a layer of SiGe having a third thickness greater than the second thickness. The method further includes removing the layers of SiGe from the first stack leaving first stacked Si nanowires spaced apart by a first distance and from the second stack leaving second stacked Si nanowires spaced apart by a second distance corresponding to the third thickness. The method further includes forming a first dielectric layer on the first nanowires and a second, thicker dielectric layer on the second nanowires.

Abstract: A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

Abstract: An organic light-emitting display apparatus including: a substrate; a display unit having a plurality of organic light-emitting devices on the substrate; an encapsulating layer sealing up the display unit; and a protective layer between the display unit and the encapsulating layer, wherein each of the plurality of organic light-emitting devices includes: a pixel electrode; an intermediate layer on the pixel electrode, the intermediate layer including an organic emission layer; and an opposite electrode on the intermediate layer, and the protective layer includes: a capping layer covering the opposite electrode; and a blocking layer on the capping layer.

Abstract: A semiconductor structure containing at least two metal resistor structures having different resistivities is provided and includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal layer portion and a first nitridized metal surface layer. A second metal resistor structure is located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content, a second metal layer portion and a second nitridized metal surface layer. The second nitrogen content of the second nitridized dielectric surface layer portion differs from the first nitrogen content of the first nitridized dielectric surface layer portion.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a gate structure, a first dielectric layer and two air gaps. The gate structure is disposed on the substrate. The gate structure has two opposite side walls. The gate structure comprises a U-shaped structure and a metal gate electrode. The U-shaped structure defines an opening toward upside, and comprises a work function layer. The metal gate electrode is disposed in the opening defined by the U-shaped structure. A level of a top surface of the U-shaped structure is lower than a level of a top surface of the metal gate electrode. The first dielectric layer is disposed on the substrate adjacent to the gate structure. Each of the two air gaps is formed between the first dielectric layer and one of the two opposite side walls of the gate structure.

Abstract: There is provided a method for processing an inner wall surface of a micro vacancy, capable of reliably etching or cleaning even if the hole provided to the substrate to be processed is narrow and deep. The substrate has a surface and a micro vacancy with an opening on the surface. An aspect ratio of the micro vacancy being at least 5, or the aspect ratio being less than 5 and a ratio of a micro vacancy volume to a surface area of the opening being at least 3. The micro vacancy is exposed to an atmosphere for forming a silicon oxide film so as to form a silicon oxide film on the inner wall surface of the micro vacancy. Subsequently a processing solution with a wettability with respect to silicon oxide is introduced into the micro vacancy so as to perform processing of the inner wall surface.

Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

Abstract: For simplifying the manufacture of a MEMS structural component including a deflectable diaphragm which spans an opening in the rear side of the structural component, and including a fixed counter-element, which is provided with passage openings, the counter-element from the base substrate of the MEMS structural component is patterned and the deflectable diaphragm is implemented in a layered structure on the base substrate. These measures are intended to improve the diaphragm properties and reduce the overall height of the MEMS structural component.

Abstract: Lateral double-diffused MOSFET transistor and fabrication method thereof are provided. A shallow trench isolation structure is formed in a semiconductor substrate. A drift region is formed in the semiconductor substrate and surrounding the shallow trench isolation structure. A body region is formed in the semiconductor substrate and distanced from the drift region. A gate structure is formed on a portion of each of the body region, the drift region, and the shallow trench isolation structure. A drain region is formed in the drift region on one side of the gate structure. A source region is formed in the body region on an other side of the gate structure. A first shallow doped region is formed in the drain region and the drift region to surround the shallow trench isolation structure.

Abstract: Embodiments of the present disclosure generally relate to data storage systems, and more particularly, to a SHE-MRAM device. The SHE-MRAM device includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. The second leads are made of a material having large spin orbit interactions and high electrical resistivity. The SHE-MRAM device further includes a periphery circuitry having multiple pairs of transistors. The multiple pairs of transistors reduce the length a current has to flow through a second lead of the plurality of second leads. By limiting the distance a current can flow through the second lead, applying excessive voltage to the second lead is avoided.

Abstract: A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiOx) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.

Abstract: An LED unit according to the invention has a resin housing which is detachably assembled to a vehicle lamp, a lead frame which has a terminal portion which is connected to an exterior terminal, an LED mounting portion and a control part mounting portion and lead frame which is provided integrally on the housing, an LED which is mounted on the LED mounting portion, and a control part which is mounted on the control part mounting portion for controlling the illumination of the LED. The lead frame has a support resin which is a resin material which holds the LED mounting portion in such a way as to surround the LED mounting portion. The lead frame is bent to a back side of the LED at areas outside the support resin, and the control part mounting portion and the terminal portion are formed respectively by the bent portions.