Abstract: A substrate processing apparatus includes: a protrusion portion formed by a side peripheral wall of a processing container which swells outward, and configured to form a vertically elongated space communicating with a processing space for accommodating a substrate holder and performing a process; a gas discharge portion provided in the vertically elongated space, and configured to discharge a process gas into the processing space; an antenna provided in the protrusion portion along a vertical direction and supplied with a high-frequency power for converting the process gas into a plasma in the vertically elongated space; and a shield extending leftward and rightward in the protrusion portion at positions closer to the processing space than the antenna and configured to shield an electric field formed by the antenna and to suppress a formation of the plasma in the processing space.

Abstract: In an embodiment, a substrate that includes a cell region and a dummy region is provided. Lower interconnection structures are formed in the cell region and the dummy region. One or more first multilayered structure patterns are formed in the cell region and one or more second multilayered structure patterns in the dummy region over the lower interconnection structures. The first multilayered structure patterns and second multilayered structure patterns extend in a first direction. Each of the second multilayered structure patterns includes an etch target layer. An insulating material layer is formed over the first multilayered structure patterns and the second multilayered structure patterns. An interlayer insulating layer that fills a space between two adjacent patterns of the first multilayered structure patterns and second multilayered structure patterns is formed by planarizing the insulating material layer. The etch target layer in each of the second multilayered structure patterns is removed.

Abstract: A deposition mask assembly includes a frame including a first opening portion and a second opening portion spaced apart from each other in a first direction, a first split mask group including a plurality of first split masks arranged on the first opening portion in a second direction crossing the first direction, and a second split mask group including a plurality of second split masks arranged on the second opening portion in the second direction, wherein a boundary between adjacent first split masks in the second direction and a boundary between adjacent second split masks in the second direction are at different positions.

Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial layer of a first conductivity type, a first semiconductor region of the first conductivity type, a second epitaxial layer of a second conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode; and a gate electrode pad. The first semiconductor region is not provided beneath the gate electrode pad.

Abstract: A process is provided for manufacturing an alkaline-based hybrid supercapacitor type battery, to an alkaline-based hybrid supercapacitor type battery, and to a process for recycling a negative electrode of an alkali-ion battery. The process for manufacturing the alkaline-based hybrid supercapacitor type battery comprises forming a negative electrode A from an electrode material B originating from a used alkali-ion battery having lost at least some of its initial capacity. Embodiments of the present disclosure are in particular applicable to the field of batteries.

Abstract: A method for repairing a bank during manufacture of an organic EL display device when a bank defect portion is produced due to collapsing of a bank, a foreign particle, or the like. The method includes: detecting a defect portion of a lengthwise bank formed over a ground substrate; and when a defect portion is detected, forming, in each of adjacent concave spaces between which the lengthwise bank having the defect portion is located, a dam partitioning the concave space into a first space in a vicinity of the bank defect portion and a second portion not in the vicinity of the bank defect portion. The shape of the dam is configured so that in ejecting organic functional layer ink in each concave space with a nozzle head, there is an ink dropping point in each of the first space and the second space.

Abstract: A diffusion agent composition that, even when a semiconductor substrate which is an object into which an impurity diffusion ingredient is to be diffused has, on a surface thereof, a three-dimensional structure having nano-scale fine voids on a surface thereof, can be evenly coated on the whole area of an inner surface of the fine voids, whereby boron can be diffused into the semiconductor substrate, and a method for manufacturing a semiconductor substrate using the composition. The composition includes an impurity diffusion ingredient and a hydrolyzable Si compound to produce a silanol group, the impurity diffusion ingredient containing a complex compound containing boron having a specific structure.

Abstract: Apparatus, systems, and processes for substrate breakage detection in a thermal processing system are provided. In one example implementation, a process can include: accessing data indicative of a plurality of temperature measurements for a substrate, the plurality of measurements obtained during a cool down period of a thermal process; estimating one or more metrics associated with a cooling model based at least in part on the data indicative of the plurality of temperature measurements; and determining a breakage detection signal based at least in part on the one or more metrics associated with the cooling model. The breakage detection signal is indicative of whether the substrate has broken during thermal processing.

Abstract: An apparatus and a method for reducing wafer warpage are provided. The method includes positioning a mold wafer structure on a stage. The mold wafer structure includes a mold layer and a stack structure positioned on a wafer. The stage includes a center region and an edge region adjacent the center region. Warpage information of the mold wafer structure is obtained. The mold wafer structure is heated by the stage based on the warpage information to reduce a warpage of the mold wafer structure. A temperature of the center region and a temperature of the edge region are different from each other. An operation test is performed on the stack structure.

Abstract: A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness.

Abstract: Silicon nitride plasma etching processes are disclosed that minimize the SiN roughness layer on a substrate having a SiN layer thereon by simultaneously introducing an oxidizer at a predetermined flow rate and an etch gas into a plasma reaction chamber containing the substrate. The etch gas has the formula CxHyFz, wherein x is 2-5, z is 1 or 2, 2x+2=y+z, and a fluorine atom is located on a terminal carbon atom of the etch gas.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers. A vertical structure extends vertically through the stack of horizontal layers, where the vertical structure has a vertical channel structure and a sidewall having formed thereon a vertical transition metal oxide (TMO) ferroelectric layer. A memory cell is formed at each of overlapping regions between the gate electrode layers and the vertical channel structure.

Abstract: Methods of connecting a read driver transistor to a PD and PU inverter of a two-port vertical SRAM via a shared GAA or a vertical cross-couple contact between a GAA of the read driver transistor and the bottom source/drain region of the PD and PU inverter and the resulting devices are provided. Embodiments include forming a first PD transistor, a first PU transistor, a second PU transistor, and a second PD transistor over a substrate; forming a first PG transistor and a second PG transistor over the substrate; forming a read transistor and a read driver transistor laterally separated in the first direction over the substrate, the read transistor and the read driver transistor adjacent to the second PG transistor and the first PD transistor, respectively; and connecting the read driver transistor, the first PD transistor, and the first PU transistor.

Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.

Abstract: Provided is a display device whose display region can be maximized. The display device includes the display region and a terminal electrode. The terminal electrode overlaps with the display region and is electrically connected to an external electrode on a non-display surface of the display region.

Abstract: A method for manufacturing a field-effect transistor includes forming an active layer of an oxide semiconductor, forming a conducting film to cover the active layer, patterning the conducting film through an etching process using an etchant to form a source electrode and a drain electrode, and performing, at least before the patterning the conducting film, a treatment on the active layer so that an etching rate of the active layer is less than an etching rate of the conducting film.

Abstract: A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.

Abstract: Devices and methods related to fabrication of shielded modules. In some embodiments, a carrier assembly can be provided for processing of packaged modules. The carrier assembly can include a plate having a first side that defines a plurality of openings, and an adhesive layer implemented on the first side of the plate. The adhesive layer can define a plurality of openings arranged to substantially match the openings of the plate, with each opening of the adhesive layer being dimensioned such that the adhesive layer is capable of providing an adhesive engagement between an underside perimeter portion of a package and a perimeter portion about the corresponding opening of the first side of the plate.

Abstract: A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.

Abstract: A mask for forming a pattern on a substrate is provided. The mask includes an anodic oxide film formed by anodizing metal, at least one transmission hole configured to vertically penetrate the anodic oxide film and formed in a corresponding relationship with the pattern, a plurality of pores formed in the anodic oxide film so as to have a smaller diameter than the transmission hole, and a magnetic material provided in each of the pores.