Patents Examined by David E. Graybill
  • Patent number: 10121875
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10121882
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10103117
    Abstract: Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a semiconductor die to the frame with respect to the fiducial mark pattern, encapsulating the semiconductor die with a passivation layer, for reconstituting the semiconductor die as a wafer level, and sequentially forming a metal seed layer, a redistribution layer, an under bump metal (UBM) seed layer, an UBM layer, and a solder ball on a bonding pad of the semiconductor die upward exposed by an opening region of the passivation layer to finish a fan-out type wafer level package.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: October 16, 2018
    Assignee: SFA Semicon Co., Ltd.
    Inventors: Hyun Hak Jung, Eun Dong Kim, Jong Won Lee, Jai Kyoung Choi, Byeong Ho Jeong
  • Patent number: 10103195
    Abstract: A pixel comprises three adjacent sub-pixels, formed by respective stacks of semi-conducting layers wherein: each sub-pixel comprises a first active layer, adapted for emitting a light at a first wavelength when an electric current passes through it; another sub-pixel comprises a second active layer, adapted for emitting a light at a second wavelength greater than the first wavelength; another sub-pixel comprises a third active layer, adapted for emitting a light at a third wavelength greater than the first wavelength and different from the second wavelength; at least one from among the second and third active layers being adapted for emitting light when it is excited by the light at the first wavelength emitted by the first active layer of the same sub-pixel. Semi-conducting structure and methods for the fabrication of such a pixel are provided.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 16, 2018
    Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Benjamin Damilano, Jean-Yves Duboz
  • Patent number: 10103278
    Abstract: A method to integrate a vertical IMPATT diode in a planar process.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 16, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaochuan Bi, Tracey L. Krakowski, Doug Weiser
  • Patent number: 10068918
    Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 4, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christian Haufe, Ingolf Lorenz, Michael Zier, Ulrich Gerhard Hensel, Navneet Jain
  • Patent number: 10050524
    Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 14, 2018
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Patent number: 10043741
    Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 7, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Guilhem Bouton
  • Patent number: 10043896
    Abstract: A transistor includes a III-N layer structure including a III-N channel layer between a III-N barrier layer and a III-N depleting layer, where the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, where the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; and where the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: August 7, 2018
    Assignee: Transphorm Inc.
    Inventors: Umesh Mishra, Rakesh K. Lal, Stacia Keller, Srabanti Chowdhury
  • Patent number: 10032646
    Abstract: An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 24, 2018
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Vage Oganesian, Kimitaka Endo
  • Patent number: 10017646
    Abstract: A composition for forming silica layer includes a silicon-containing polymer and a solvent, wherein a weight average molecular weight of the silicon-containing polymer ranges from about 2,000 to about 100,000 and a branching ratio (a) of the silicon-containing polymer calculated by Equation 1 ranges from about 0.25 to about 0.50. ?=k·Ma??[Equation 1] In Equation 1, ? is an intrinsic viscosity of a silicon-containing polymer, M is an absolute molecular weight of a silicon-containing polymer, a is a branching ratio, and k is an intrinsic constant.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: July 10, 2018
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Sooyeon Sim, Jin-Hee Bae, TaekSoo Kwak, Yonggoog Kim, Jingyo Kim, Kunbae Noh, Huichan Yun, Jiho Lee, Byeong Gyu Hwang
  • Patent number: 10020403
    Abstract: A low-power-consuming semiconductor device that can store analog data stably and very accurately is provided at low cost. The semiconductor device includes a power supply portion, a sensor portion, and a memory element portion. The sensor portion acquires analog data. The memory element portion stores the analog data. A channel formation region of a transistor included in the memory element portion is formed in an oxide semiconductor film. The semiconductor device does not include an analog/digital converter circuit and has functions of measuring and storing analog data.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: July 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hikaru Tamura
  • Patent number: 10002860
    Abstract: An integrated circuit includes at least one cell. The at least one cell includes a cell region defined by a cell boundary; a power line structure extending in a first direction parallel to and along the cell boundary and including a first power line extending in the first direction along the cell boundary, a plurality of metal islands spaced apart from one another over the first power line in the first direction, and a second power line extending in the first direction over the plurality of metal islands; and a signal line structure disposed in the cell region at the same level as the first power line and the plurality of metal islands. Separation distances between each of the plurality of metal islands and a part of the signal line structure at the same level as the plurality of metal islands are equal to or greater than a critical separation distance.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 19, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Raheel Azmat
  • Patent number: 10002763
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing a support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the semiconductor substrate.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: June 19, 2018
    Assignee: Soitec
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
  • Patent number: 9997445
    Abstract: A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 12, 2018
    Assignee: NXP USA, INC.
    Inventors: Kai Yun Yow, Chee Seng Foong, Bihua He, Navas Khan Oratti Kalandar, Lan Chu Tan, Yuan Zang
  • Patent number: 9997703
    Abstract: A resistive memory device includes a bottom electrode and a top electrode sandwiching a switching layer. The device also includes a field enhancement (FE) feature that extends from the bottom electrode either into the switching layer or is covered by switching layer and that is to enhance an electric field generated by the two electrodes to thereby confine a switching area of the device at the FE feature. The device further includes a planar interlayer dielectric surrounding the device, for supporting the top electrode. A method of making a resistive memory device, employing in-situ vacuum deposition of all layers, is also provided.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: June 12, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Si-Ty Lam, Xia Sheng, Richard H. Henze, Zhang-Lin Zhou
  • Patent number: 9991410
    Abstract: A method of manufacturing a lead wire for a solar cell includes heating a wire material by a direct resistance heating or by an induction heating to reduce a 0.2% proof stress of the wire material while conveying the wire material and plating the wire material that is in a heated condition obtained by the direct resistance heating or by the induction heating while further conveying the wire material. An apparatus is configured to implement the method, and includes a plating bath, a conveyor mechanism configured to convey the wire material, a heater configured to heat the wire material, and a controller configured to control the conveyor mechanism and the heater.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: June 5, 2018
    Assignee: NETUREN CO., LTD.
    Inventors: Yoshiki Seto, Kunihiro Kobayashi, Nobumoto Ishiki, Hisaaki Watanabe
  • Patent number: 9960034
    Abstract: A method, which forms an air-bubble-free thin film with a high-viscosity fluid resin, initially dispenses the fluid resin on an outer region of a semiconductor wafer while the semiconductor wafer is spinning, and then dispenses the fluid resin onto the center of the semiconductor wafer after the semiconductor wafer has stopped spinning.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: May 1, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandra Zheng, Mark James Smiley, Douglas Jay Levack, Ronald Dean Powell
  • Patent number: 9953829
    Abstract: A semiconductor manufacturing method includes setting a relative position between first through holes of a first plate-shaped part and second through holes of a second plate-shaped part to a first relative position. The method includes supplying a first gas containing a component of the first film onto the semiconductor substrate in a reactor through the first through holes not closed with the second plate-shaped part, to form the first film on the semiconductor substrate. The method includes relatively moving the first plate-shaped part and the second plate-shaped part to change the relative position to a second relative position. The method includes supplying a second gas containing a component of the second film onto the semiconductor substrate through the first through holes not closed with the second plate-shaped part, to laminate the second film on the first film.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hideaki Masuda, Nobuhide Yamada
  • Patent number: 9947721
    Abstract: Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. To prevent this thermal disturb effect, memory cells may be separated from one another by thermally insulating regions that include one or several interfaces. The interfaces may be formed by layering different materials upon one another or adjusting the deposition parameters of a material during formation. The layers may be created with planar thin-film deposition techniques, for example.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 17, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Paolo Fantini