Patents Examined by David Foster
  • Patent number: 6351390
    Abstract: A process is given for permitting the application to a substrate (2) of a microsystem or transducer (1) having a first partial surface (13), whose interaction with the environment is to be possible, and a second partial surface (14), which is to be protected against external influences. The substrate (2) is prepared, a passage point (20) being produced in said substrate (2). The microsystem (1) and substrate (2) are so mutually positioned that the first partial surface (13) faces the substrate (2) and that the passage point (20) in the substrate (2) and the first partial surface (13) come to rest opposite one another. Contacts (50, 51.1, 51.2) are produced by flip-chip technology. A sealing contact (51.1, 51.2) seals the second partial surface (14) against external influences. A gap (3) between the microsystem (1) and substrate (2) is filled with a filling material (30). A selective cover (24) over the passage point (20) keeps undesired external influences away from the first partial surface (13).
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: February 26, 2002
    Assignee: Laboratorium fur Physikalische Elektronik Institut fur Quantenelektronik
    Inventors: Felix Mayer, Oliver Paul
  • Patent number: 6351389
    Abstract: A method and apparatus for packaging an electronic device, such as an integrated circuit chip (8), includes an intermediate device carrier (6) with a substantially planar upper surface (16) and a plurality of bonding pads (18) for coupling the carrier to the integrated circuit chip. A ceramic ring (38) is attached to the upper surface of the device carrier and a thermally conductive cover plate (36) is attached to the ceramic ring to form an inner cavity for receiving the chip therein. The ceramic ring comprises a material with a coefficient of thermal expansion substantially similar to or as the same as the device carrier to minimize stress therebetween during thermal expansion or contraction of the package device. The thermally conductive cover plate provides a path for dissipating heat generated during electrical operations of the chip.
    Type: Grant
    Filed: May 7, 1996
    Date of Patent: February 26, 2002
    Assignee: Sun Microsystems, Inc.
    Inventor: Deviprasad Malladi
  • Patent number: 6347039
    Abstract: A memory module includes a plurality of semiconductor memory devices mounted on a printed wiring board (PWB); longitudinal contact terminals that are for connection to a computer mother board and are arranged along at least one longitudinal edge of the PWB; and transverse contact terminals that are for connection to the computer mother board and are arranged along at least one transverse edge of the PWB. A socket for the module includes at least one longitudinal part into which the longitudinal contact terminals are inserted and at least one transverse part into which the transverse contact terminals are inserted. Each transverse socket part can be mounted on a pivot attached to the longitudinal part and rotated to engage a PWB inserted in the longitudinal part. Alternatively, each transverse part can be a flexible circuit carrier.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: February 12, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung Joon Lee
  • Patent number: 6344976
    Abstract: An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: February 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Schoenfeld, Jerry M. Brooks
  • Patent number: 6344973
    Abstract: The invention relates to a power module with a circuit arrangement provided with active semiconductor components and passive components and with a circuit substrate, whereby at least a portion of the active semiconductor components are soldered onto a DCB substrate and at least a portion of the passive components are printed in thick film technology on at least one ceramic substrate. The upper side of the DCB substrate is structured to form track conductors and connecting surfaces for receiving the active semiconductor components and passive components of the circuit arrangement. On the ceramic substrate, for each passive component, a first print layer is printed in thick film technology and at least one contact surface as additional print layer laterally adjoining the first print layer.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: February 5, 2002
    Assignee: Alcatel
    Inventors: Hans-Peter Feustel, Friedrich Loskarn, Reinhard Rückert
  • Patent number: 6343019
    Abstract: An apparatus and method wherein an outer die is mounted on an inner die to form a stack which is mounted on a first surface of a substrate, such as a circuit board, the stack may be mounted filly or partially recessed in a recess which is formed in a first surface of the substrate which is dimensioned for receiving at least a portion of a die therein, and where an aperture may be formed in the recess extending through the substrate to a second side thereof for wire bonding the inner die to the substrate.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: January 29, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Chad A. Cobbley
  • Patent number: 6341060
    Abstract: An optical disk drive assembly includes a hollow housing, an optical disk drive, and a control panel. The hollow housing has a bottom wall, two opposite side walls extending upwardly from two opposite sides of the bottom wall, a rear wall extending upwardly from a rear end of the bottom wall, and a front opening formed at a front end of the bottom wall and opposed to the rear wall. The optical disk drive is mounted inside the hollow housing. The optical disk drive is spaced apart from and is disposed above the bottom wall to define a clearance therebetween. The control panel is movably received in the clearance. The control panel has a front end, and a plurality of control keys disposed adjacent to the front end of the control panel and connected electrically to the optical disk drive for manipulation of the optical disk drive.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: January 22, 2002
    Assignee: Compal Electronics, Inc.
    Inventor: Kuei-Chu Chuang
  • Patent number: 6341070
    Abstract: This invention discloses a wafer level packaging method and configuration. This improved wafer level package includes a processed wafer mounted on a first printed circuit board (PCB) carrier. The processed wafer mounted on the PCB carrier board includes a plurality of separated integrated circuit (IC) chips divided by scribe-line gaps wherein each of these scribe-line gaps is filled with flexible gap-filling insulation material. In another preferred embodiment, the wafer-level package further includes a second PCB carried board composed of same material as the first PCB carrier board mounted on top of the wafer. In another preferred embodiment, the wafer-level package, which having the first and the second PCB carrier boards further includes a plurality of connection via penetrating through the first and the second PCB carried board for forming electric connection to the IC chips separated by the scribe-line gaps.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: January 22, 2002
    Inventor: Ho-Yuan Yu
  • Patent number: 6335867
    Abstract: Apparatus for interconnecting logic boards is provided with a backplane, a plurality of logic boards connected to the backplane, and a plurality of interconnecting boards, connected to the backplane, for interconnecting the plurality of logic boards. In the apparatus, the plurality of logic boards are connected to the backplane with the logic boards in vertical position at right angles with the interconnecting boards and a specified distance away from the interconnecting boards.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: January 1, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Ishibashi, Takehisa Hayashi, Tsutomu Goto, Akira Yamagiwa, Tsuyoshi Watanabe
  • Patent number: 6330165
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: December 11, 2001
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Patent number: 6327159
    Abstract: A wireform bracket provides a simple, elegant, low-cost solution for managing a large number of cables, while also allowing ample airflow at the back of a computer system. A wireform bracket in accordance with the present invention includes a plurality of bends, with each bend proximate a connector on the backplane of a computer system when the wireform bracket is attached to the back of the computer system. As cables are connected to the back of the computer system, each cable is fastened to the nearest bend using a tie-wrap, or some other cable fastening method known in the art. The present invention minimizes potential strain at the connectors by shifting any strain to the point at which the cable is attached to the wireform bracket, while also minimizing the disruption of airflow in the area immediately behind a computer system. In one embodiment, a wireform cable is formed from a ⅛ inch thick piece of steel wire, though other materials and thicknesses may be Mused.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: December 4, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Douglas Davies, Michael Wortman
  • Patent number: 6326553
    Abstract: A flexible circuit board which can be assembled into a head gimbal assembly of a hard disk drive. The flexible circuit board may have a conductive tab that is electrically connected to a pre-amp pad and a head pad of the circuit board. The head pad may be connected to a head. The conductive tab may be grounded during handling of the flexible circuit board. Any electrostatic discharge on the head may be grounded through the conductive tab.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: December 4, 2001
    Assignee: Samsung Electronics, Co., Ltd
    Inventors: Pyongwon Yim, Andrew S. Kao, Hyung Jai Lee
  • Patent number: 6324071
    Abstract: A stacked printed circuit board memory module in which a plurality of daughter circuit boards can be stacked onto a primary circuit board. The primary board and each of the plurality of daughter boards have electronic memory ICs mounted on the respective surfaces. The primary board and each of the daughter boards have mounted connectors so that the boards can be electrically and mechanically interconnected with another board.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Rick Weber, James Howarth, Corey Larsen
  • Patent number: 6324068
    Abstract: The contours of openings of a solder resist defining exposed portions of electrode pads and the contours of openings of the solder resist defining the contours of register or patterns are simultaneously formed by photolithography using the same mask pattern. As a result, the patterns for registration can be easily formed on a main board or circuit boards. Also, it is possible to increase the positional accuracy of the register or patterns relative to the positions of the electrode pads.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: November 27, 2001
    Assignee: Citizen Watch Co., Ltd.
    Inventors: Kiyoshi Shimizu, Yoshihiro Ishida
  • Patent number: 6324052
    Abstract: A personal computing device, such as a lap-top computer, has a body with a keyboard, a lid with a display screen hinged to the body, a resonant panel loudspeaker carried by the lid and an acoustic waveguide on the lid to direct acoustic output from the loudspeaker. The waveguide comprises a member mounted on the lid, the member being movable on the lid from a retracted/closed position to an advanced/open position.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: November 27, 2001
    Assignee: New Transducers Limited
    Inventors: Henry Azima, Martin Colloms, Norman Crocker, Martin Roberts
  • Patent number: 6324066
    Abstract: A surface mountable electronic device (1) includes a mount (2), an electrical component (3) supported by the mount and two external terminals (5, 5a) electrically coupled to the component, the external terminals being mounted on the mount at diagonally opposite corners. The device is orientation dependent relative to solder pads (6) on a substrate (7) in that the device can be rotated through 90° about a central axis (8) in either direction and still allow alignment between the external terminals of the device and the substrate solder pads.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: November 27, 2001
    Assignee: Motorola, Inc.
    Inventors: Ban Choong Poh, Kean Seong Hooi, Lay Choo Ch'ng
  • Patent number: 6320753
    Abstract: Integrated circuit board combining external contact zones and an antenna to receive data transmitted by a terminal, and process for manufacturing such a board. The integrated circuit board in accordance with the invention comprises a single integrated circuit connected both to an antenna by connection terminals and to external contact zones by other connection terminals; the antenna is arranged between a support and a strip; the above-mentioned connection terminals are arranged opposite the corresponding connection ends of the integrated circuit and are respectively connected to them; the integrated circuit is arranged by a process know by the name “flip-chip” in a cavity in which the connection terminals of the antenna and those of the external contact zones are accessible. The board in accordance with the invention may by used both with a reader connected to the external contact zones or with a terminal transmitting data without contacts, by means of the antenna.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: November 20, 2001
    Assignee: Oberthur Card Systems SA
    Inventor: Francois Launay
  • Patent number: 6320754
    Abstract: A device that reduces the interfacial stress caused by differential thermal expansion in an IC/PC board assembly can be created by attaching an annular part, that has a higher coefficient of thermal expansion, to the IC at an elevated temperature. When the assembly cools the annular part contracts and compresses the IC, increasing the change in size of the IC and reducing the stress in the IC/PC joint.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: November 20, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Walter J Dauksher, Pedro F Engel
  • Patent number: 6320750
    Abstract: A line replaceable module (LRM) configured with a plurality of mini-modules, each of which have relatively higher contact densities than currently available LRMs with the same form factor, for example, a Standard Electrical Module-Size E (SEM-E) form factor. The mini-modules are significantly less expensive than an entire module allowing such mini-modules to be disposable, eliminating relatively costly fault diagnostics and repair. Each mini-module includes a printed circuit board which includes a rigid primary portion, a rigid secondary portion and flexible portion interconnecting the primary and secondary portions. The rigid secondary portion may be configured to provide dual-sided interconnection to a backplane data bus. Use of the dual-sided rigid secondary portion provides for generous spacing for contact densities much higher than known contact densities for LRMs with the same form factor. The rigid primary portion carries the components forming the LRM.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: November 20, 2001
    Assignee: TRW Inc.
    Inventors: Barton G. Shaler, Donald A. Porter, Milton F. Damerow
  • Patent number: 6317331
    Abstract: A wiring substrate with reduced thermal expansion. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or a BGA package. The wiring substrate has a thermal expansion reduction insert in a thermal expansion stress region where the integrated circuit is mounted. The thermal expansion reduction insert may extend a selected distance from the edge or edges of the integrated circuit attachment area, or stop a selected distance from the edge or edges of the integrated circuit attachment area, or be essentially equal to the integrated circuit attachment area. The thermal expansion reduction insert reduces the thermal expansion of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: November 13, 2001
    Assignee: Kulicke & Soffa Holdings, Inc.
    Inventors: Sundar Kamath, David Chazan, Solomon I. Beilin