Abstract: A method of is provided as a process of substrate lift-off. The present invention is mainly used for a group III-V solar cell, which has the highest power generation efficiency. An original sacrificial layer is changed into an AlAs oxide layer, which is transformed into an AlOx sacrificial layer after wet oxidation. The sacrificial layer is then soaked in an oxide-relief solution for etching. Thus, the lift-off process of a GaAs substrate can be harmlessly processed to the complex group III-V solar cell. The GaAs substrate can be recycled to be effectively further reused in photovoltaic devices with reduced cost.

Abstract: The present application discloses a display panel. The display panel includes a base substrate; a display unit on the base substrate; and an encapsulating layer on a side of the display unit distal to the base substrate and encapsulating the display unit. The encapsulating layer includes a first inorganic encapsulating layer on a side of the display unit distal to the base substrate; and a first organic encapsulating layer and a second organic encapsulating layer on a side of the first inorganic encapsulating layer distal to the display unit. Each of the first organic encapsulating layer and the second organic encapsulating layer is in contact with the first inorganic encapsulating layer. The first organic encapsulating layer has a Young's modulus lower than that of the second organic encapsulating layer.

Abstract: The present invention relates to a switching device, a method of fabricating the same, and a nonvolatile memory device including the same. A switching device according to an embodiment of the present invention includes a first electrode; a second electrode; and a switching film which is disposed between the first electrode and the second electrode, and includes an electrically insulating matrix and a conductive path formed in the electrically insulating matrix. In this embodiment, the conductive path includes crystalline metal clusters dispersed in the electrically insulating matrix and a metal bridge connecting adjacent crystalline metal clusters.

Abstract: An electrical distribution grid energy management and router device, or GER device, may be installed in a distribution grid, and route power from power supply to one or more power consumers. The GER devices described herein may provide platforms to add one or more features to a distribution transformer, provide additional features and benefits to both the utility company and end consumer, and may serve as a platform for providing other features, such as communications services, local and remote management, and intelligence to components of the distribution grid. A GER device may include sensors to measure electrical properties of incoming and outgoing power, and may include an electrical circuit layer having a central DC power stage. A GER device may include a physical layer providing a communications platform for one or more communication devices that may communicate with other GER devices to form a micro-grid, a utility, power consumers, third parties, and other electrical devices.

Abstract: In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.

Abstract: A video-wall module is disclosed. In an embodiment a video-wall module includes a printed-circuit board, a plurality of light-emitting diode chips arranged at the printed-circuit board, a circuit chip fixed to the printed-circuit board, wherein the circuit chip is connected with electrical connections of the light-emitting diode chips in order to electrically actuate the light-emitting diode chips and a housing for the circuit chip at least partially formed by the printed circuit board, wherein the light-emitting diode chips are divided into a first area and a first edge area surrounding the first area, and wherein the light-emitting diode chips in the first area comprise a smaller radiation wavelength than the light-emitting diode chips in the first edge area on average at the same temperature.

Abstract: A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

Abstract: A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.

Abstract: Devices and methods are provided for fabricating field-effect transistors having source/drain extension contacts to provide reduced parasitic resistance in electrical paths between source/drain layers and active channel layers surrounded by gate structures of the field-effect transistor devices. For example, in a nanosheet field-effect transistor device having embedded gate sidewall spacers which are disposed between end portions of active nanosheet channel layers and serve to insulate source/drain layers from a metal gate structure, epitaxial source/drain extension contacts are disposed between the embedded gate sidewall spacers and active nanosheet channel layers, and on sidewall surfaces of the active nanosheet channel layers. Epitaxial source/drain layers are grown starting on exposed surfaces of the epitaxial source/drain extension contacts.

Abstract: The present disclosure provides a fabricating method of an array substrate, comprising: forming a pattern comprising a light shading member; spreading an organic material solution; solidifying the organic material solution, to form a buffer layer; forming a pattern of an active layer on the buffer layer, wherein a position of the active layer corresponds to a position of the light shading member; and forming a gate pattern, where the gate pattern is located on the active layer and is insulated from the active layer. Correspondingly, the present disclosure further provides an array substrate and a display device.

Abstract: An epitaxial conversion element, a method for producing an epitaxial conversion element, a radiation emitting RGB unit and a method for producing a radiation emitting RGB unit are disclosed. In an embodiment an epitaxial conversion element includes a green converting epitaxial layer configured to convert electromagnetic radiation from a blue spectral range into electromagnetic radiation of a green spectral range and a red converting epitaxial layer configured to convert electromagnetic radiation from the blue spectral range into electromagnetic radiation of a red spectral range, wherein the green converting epitaxial layer and the red converting epitaxial layer are based on a phosphide compound semiconductor material, and wherein the green converting epitaxial layer and the red converting epitaxial layer are in different main extension planes which are parallel to each other.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.

Abstract: The present invention provides an array substrate comprising a substrate, an inorganic layer formed on the substrate, a metal wiring formed on the inorganic layer, and an organic layer on the inorganic layer and covering the metal wiring; wherein the metal wiring and/or the inorganic layer include a bending performance enhancement structure. In this invention, by means of providing the bending performance enhancement structure in the metal wiring and/or the inorganic layer, the stress in the bending region is released when the flexible display is bent, so as to prevent the bending region from fracture or damage and improve the bending performance.

Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.