Abstract: A panel is provided, including a first conductive pattern and a second conductive pattern. The first conductive pattern includes a first portion and a second portion; the second conductive pattern connects the first portion to the second portion, and an insulation pattern substantially covering a side surface of the second conductive pattern. The insulation pattern is formed by thermally treating a mask pattern of an insulation material. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least one metal layer, where the at least one metal layer interconnecting the first transistors; a plurality of first logic gates including the at least one metal layer interconnecting the first transistors; a plurality of second transistors atop the at least one metal layer; a plurality of third transistors atop the second transistors; a top metal layer atop the third transistors; and a memory array including wordlines, where the memory array includes at least four rows by four columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second transistors or at least one of the third transistors.

Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.

Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.

Abstract: A semiconductor device includes a semiconductor element, an internal electrode connected to the semiconductor element, a sealing resin covering the semiconductor element and a portion of the internal electrode, and an external electrode exposed from the sealing resin and connected to the internal electrode. The internal electrode includes a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface facing the back surface of the semiconductor element and a wiring layer back surface facing opposite from the wiring layer front surface in the thickness direction. The columnar portion protrudes in the thickness direction from the wiring layer front surface. The columnar portion has an exposed side surface facing in a direction perpendicular to the thickness direction. The external electrode includes a first cover portion covering the exposed side surface.

Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

Abstract: A bonding material including a phenoxy resin thermoplastic component, and a carbon black filler component. The carbon black filler component is present in an amount greater than 1 wt. %. The carbon black filler converts the phenoxy resin thermoplastic component from a material that transmits infra-red (IR) wavelengths to a material that absorbs a substantial portion of infra-red (IR) wavelengths.

Abstract: A display device including a display panel is provided. The display panel includes a first substrate, a first transistor, a sensing element, a first conductive layer and a second conductive layer. The first transistor is disposed on the first substrate. The sensing element is disposed on the first substrate and electrically connected to the first transistor. The sensing element includes a first-type semiconductor layer, an insulation layer and a second-type semiconductor layer. The insulation layer is disposed on the first-type semiconductor layer. The second-type semiconductor layer is disposed on the insulation layer. The first conductive layer is disposed between the first substrate and the sensing element, and the first conductive layer contacts with and electrically connected to the first-type semiconductor layer. The second conductive layer is disposed on the sensing element, and the second conductive layer contacts with and electrically connected to the second-type semiconductor layer.

Abstract: Described herein is a technique capable of improving a quality of a substrate processing. According to one aspect of the technique described herein, there is provided a method of manufacturing a semiconductor device including: (a) receiving substrate data including at least one of a stacked number of layers of a device formed on a substrate and a structure of the device; (b) setting an apparatus parameter corresponding to the substrate data; (c) supporting the substrate corresponding to the substrate data above a substrate support; (d) elevating a temperature of the substrate based on the apparatus parameter while the substrate is separated from a surface of the substrate support; (e) placing the substrate on the substrate support after (d); and (f) processing the substrate in a process chamber.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit formed by two cross-coupled inverters, and a pass-gate transistor coupling an output of the latch circuit to a bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact. The logic cell includes a transistor. A second source/drain region of the transistor is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact. The first and second vias are the same height. The interconnect line and the bit line are formed in the same metal layer, and the bit line is thicker than the interconnect line.

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

Abstract: An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.

Abstract: A current source includes a substrate, a base region of a first doping type formed in the substrate, an emitter region of a second doping type formed in the substrate and surrounding the base region, a first collector region of the second doping type formed in the base region, and at least one second collector region of the second doping type formed in the base region, wherein the emitter region includes a deep-well portion and an extending portion, the deep-well portion situated beneath the base region, the extending portion laterally surrounding the base region, the extending portion joined at its bottom to the deep-well portion, the extending portion being flush at its top with a top surface of the substrate. A method of forming the current source is also disclosed.

Abstract: An array substrate includes gate lines made of a first metal film, source lines made of a second metal film disposed such that a gate insulating film is interposed between the second metal film and the first metal film, the source lines extending to intersect the gate lines, auxiliary lines made of the first metal film, the auxiliary lines being arranged such that a pair of auxiliary lines sandwich the gate line therebetween and extending in parallel with the source lines to at least partly overlap the source lines, respectively, and bridge lines made of a third metal film disposed such that a first inter-layer film located opposite to the gate insulating film is interposed between the third metal film and the second metal film, the bridge lines being arranged to lie astride the gate lines, respectively, to electrically connect the source lines to pairs of the auxiliary lines.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.

Abstract: A method of processing a plate-shaped workpiece that includes layered bodies containing metal which are formed in superposed relation to projected dicing lines, includes the steps of holding the workpiece on a holding table, and thereafter, cutting the workpiece along the projected dicing lines with an annular cutting blade, thereby separating the layered bodies. The cutting blade has a groove defined in a face side or a reverse side of an outer peripheral portion thereof that cuts into the workpiece in the step of cutting the workpiece. The step of cutting the workpiece includes the step of cutting the workpiece while supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.

Abstract: A light source device includes a package and a substrate. The package includes first and second electrodes. The first electrode has first and second parts separated from each other by a first separation region on a lower surface side of the first electrode while the first part is continuous with the second part on an upper surface side. The substrate includes a pair of wiring members. Lower surfaces of the first and second parts face and are mounted on an upper surface of one of the wiring members. A lower surface of the second electrode faces and is mounted on an upper surface of the other of the wiring members. A region of the substrate facing the first separation region has solder wettability lower than solder wettability of the upper surface of the one of the wiring members facing the first part and the second part of the first electrode.